该模块主要完成并串转换功能。其中system_clk是输入并行时钟的频率，它是串行时钟serial_clk的八倍。byte_data_en是输入并行数据使能信号，byte_data是输入并行数据。serial_data是转换后的串行数据，bit_data_enable是串行数据有效信号。,The module main is completed and the string conversion functions. System_clk which is an input parallel clock frequency, it is the serial clock serial_clk eight times. byte_data_en is a parallel data input enable signal, byte_data is a parallel data input. serial_data is converted serial data, bit_data_enable is the serial data signal.