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文件名称:uart8.zip

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-09-04
  • 文件大小：
    856.5kb
  • 已下载：
    0次
  • 提 供 者：
    张***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。,Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
相关搜索： UART IMplementation in FPGA buffer in vhdl UART VHDL communication vhdl

(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart8/
uart8/component/
uart8/component/Actel/
uart8/component/Actel/DirectCore/
uart8/component/Actel/DirectCore/COREUART/
uart8/component/Actel/DirectCore/COREUART/3.1.103/
uart8/component/Actel/DirectCore/COREUART/3.1.103/coreparameters.v
uart8/component/Actel/DirectCore/COREUART/3.1.103/COREUART.cxf
uart8/component/Actel/DirectCore/COREUART/3.1.103/mti/
uart8/component/Actel/DirectCore/COREUART/3.1.103/mti/lib_vlog_obs/
uart8/component/Actel/DirectCore/COREUART/3.1.103/mti/lib_vlog_obs/COREUART_LIB/
uart8/component/Actel/DirectCore/COREUART/3.1.103/mti/lib_vlog_obs/COREUART_LIB/_info
uart8/component/Actel/DirectCore/COREUART/3.1.103/mti/scripts/
uart8/component/Actel/DirectCore/COREUART/3.1.103/mti/scripts/wave_vlog.do
uart8/component/Actel/DirectCore/COREUART/3.1.103/rtl/
uart8/component/Actel/DirectCore/COREUART/3.1.103/rtl/vlog/
uart8/component/Actel/DirectCore/COREUART/3.1.103/rtl/vlog/core_obfuscated/
uart8/component/Actel/DirectCore/COREUART/3.1.103/rtl/vlog/core_obfuscated/Clock_gen.v
uart8/component/Actel/DirectCore/COREUART/3.1.103/rtl/vlog/core_obfuscated/CoreUART.v
uart8/component/Actel/DirectCore/COREUART/3.1.103/rtl/vlog/core_obfuscated/fifo_256x8_pa3.v
uart8/component/Actel/DirectCore/COREUART/3.1.103/rtl/vlog/core_obfuscated/Rx_async.v
uart8/component/Actel/DirectCore/COREUART/3.1.103/rtl/vlog/core_obfuscated/Tx_async.v
uart8/component/Actel/DirectCore/COREUART/3.1.103/rtl/vlog/test/
uart8/component/Actel/DirectCore/COREUART/3.1.103/rtl/vlog/test/verif/
uart8/component/Actel/DirectCore/COREUART/3.1.103/rtl/vlog/test/verif/testbnch.v
uart8/component/work/
uart8/component/work/UartIP/
uart8/component/work/UartIP/testbench.v
uart8/component/work/UartIP/UartIP.cxf
uart8/component/work/UartIP/UartIP.sdb
uart8/component/work/UartIP/UartIP.v
uart8/constraint/
uart8/constraint/uart_ctrl.sdc
uart8/coreconsole/
uart8/coreconsole/UartIP/
uart8/designer/
uart8/designer/impl1/
uart8/designer/impl1/designer.log
uart8/designer/impl1/designer_genhdl.log
uart8/designer/impl1/PLL_1536.ide_des
uart8/designer/impl1/PLL_33.ide_des
uart8/designer/impl1/simulation/
uart8/designer/impl1/UartIP.ide_des
uart8/designer/impl1/uart_control.ide_des
uart8/designer/impl1/uart_ctrl.adb
uart8/designer/impl1/uart_ctrl.dtf/
uart8/designer/impl1/uart_ctrl.dtf/verify.log
uart8/designer/impl1/uart_ctrl.ide_des
uart8/designer/impl1/uart_ctrl.pdb
uart8/designer/impl1/uart_ctrl.pdb.depends
uart8/designer/impl1/uart_ctrl.stp
uart8/designer/impl1/uart_ctrl.tcl
uart8/designer/impl1/uart_ctrl_fp/
uart8/designer/impl1/uart_ctrl_fp/$$FlashPro_08166.L$$
uart8/designer/impl1/uart_ctrl_fp/$$FlashPro_08424.L$$
uart8/designer/impl1/uart_ctrl_fp/projectData/
uart8/designer/impl1/uart_ctrl_fp/projectData/uart_ctrl.pdb
uart8/designer/impl1/uart_ctrl_fp/uart_ctrl.log
uart8/designer/impl1/uart_ctrl_fp/uart_ctrl.pro
uart8/designer/impl1/uart_initial.ide_des
uart8/hdl/
uart8/hdl/interface.v
uart8/hdl/uart_control.v~RF14e5b17.TMP
uart8/hdl/uart_control.v~RF1a74220.TMP
uart8/hdl/uart_control.v~RF58c8e1.TMP
uart8/hdl/uart_ctrl.v
uart8/hdl/uart_ctrl.v.bak
uart8/hdl/uart_ctrl.v~RF105819e.TMP
uart8/hdl/uart_ctrl.v~RF17d802f.TMP
uart8/hdl/uart_ctrl.v~RF1ec6b34.TMP
uart8/hdl/uart_ctrl.v~RF275e2bb.TMP
uart8/hdl/uart_initial.v
uart8/hdl/uart_initial.v~RF1057e04.TMP
uart8/phy_synthesis/
uart8/simulation/
uart8/simulation/modelsim.ini
uart8/simulation/modelsim.ini.sav
uart8/simulation/modelsim.log
uart8/simulation/postsynth/
uart8/simulation/postsynth/@c@o@r@e@u@a@r@t_0s_0s_15s/
uart8/simulation/postsynth/@c@o@r@e@u@a@r@t_0s_0s_15s/verilog.psm
uart8/simulation/postsynth/@c@o@r@e@u@a@r@t_0s_0s_15s/_primary.dat
uart8/simulation/postsynth/@c@o@r@e@u@a@r@t_0s_0s_15s/_primary.dbs
uart8/simulation/postsynth/@c@o@r@e@u@a@r@t_0s_0s_15s/_primary.vhd
uart8/simulation/postsynth/@clock_gen/
uart8/simulation/postsynth/@clock_gen/verilog.psm
uart8/simulation/postsynth/@clock_gen/_primary.dat
uart8/simulation/postsynth/@clock_gen/_primary.dbs
uart8/simulation/postsynth/@clock_gen/_primary.vhd
uart8/simulation/postsynth/@p@l@l_33/
uart8/simulation/postsynth/@p@l@l_33/verilog.psm
uart8/simulation/postsynth/@p@l@l_33/_primary.dat
uart8/simulation/postsynth/@p@l@l_33/_primary.dbs
uart8/simulation/postsynth/@p@l@l_33/_primary.vhd
uart8/simulation/postsynth/@rx_async_0s_0s_1s_2s/
uart8/simulation/postsynth/@rx_async_0s_0s_1s_2s/verilog.psm
uart8/simulation/postsynth/@rx_async_0s_0s_1s_2s/_primary.dat
uart8/simulation/postsynth/@rx_async_0s_0s_1s_2s/_primary.dbs
uart8/simulation/postsynth/@rx_async_0s_0s_1s_2s/_primary.vhd
uart8/simulation/postsynth/@tx_async_0s_0s_1s_2s_3s_4s_5s_6s/
uart8/simulation/postsynth/@tx_async_0s_0s_1s_2s_3s_4s_5s_6s/verilog.psm
uart8/simulation/postsynth/@tx_async_0s_0s_1s_2s_3s_4s_5s_6s/_primary.dat
uart8/simulation/postsynth/@tx_async_0s_0s_1s_2s_3s_4s_5s_6s/_primary.dbs
uart8/simulation/postsynth/@tx_async_0s_0s_1s_2s_3s_4s_5s_6s/_primary.vhd
uart8/simulation/postsynth/@uart@i@p/
uart8/simulation/postsynth/@uart@i@p/verilog.psm
uart8/simulation/postsynth/@uart@i@p/_primary.dat
uart8/simulation/postsynth/@uart@i@p/_primary.dbs
uart8/simulation/postsynth/@uart@i@p/_prim

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