文件名称:UART.rar
-
所属分类:
- 标签属性:
- 上传时间:2012-09-04
-
文件大小:279.11kb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
主芯片:Actel的FPGA030,Verilog语言,串口发送和接收的例程,开发环境:LiberoIDE 8.5,The main chip: Actel' s FPGA030, Verilog language, the serial port to send and receive routines, development environment: LiberoIDE 8.5
相关搜索: uart actel verilog
ACTEL
verilog uart
verilog actel
verilog uart actel
actel fpga0
uart verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
designer/impl1/designer.log
designer/impl1/uart_test.adb
designer/impl1/uart_test.dtf/verify.log
designer/impl1/uart_test.ide_des
designer/impl1/uart_test.pdb
designer/impl1/uart_test.pdb.depends
designer/impl1/uart_test.tcl
designer/impl1/uart_test_fp/$$FlashPro_FPBBALTLPT1.L$$
designer/impl1/uart_test_fp/projectData/uart_test.pdb
designer/impl1/uart_test_fp/uart_test.log
designer/impl1/uart_test_fp/uart_test.pro
hdl/rec.v
hdl/send.v
hdl/uart_test.v
simulation/modelsim.ini
simulation/modelsim.ini.sav
smartgen/smartgen.aws
synthesis/.recordref
synthesis/backup/uart_test.srr
synthesis/run_options.txt
synthesis/stdout.log
synthesis/syntmp/sap.log
synthesis/syntmp/uart_test.msg
synthesis/syntmp/uart_test.plg
synthesis/syntmp/uart_test_flink.htm
synthesis/syntmp/uart_test_srr.htm
synthesis/syntmp/uart_test_toc.htm
synthesis/traplog.tlg
synthesis/uart_test.areasrr
synthesis/uart_test.edn
synthesis/uart_test.fse
synthesis/uart_test.htm
synthesis/uart_test.map
synthesis/uart_test.sap
synthesis/uart_test.sdf
synthesis/uart_test.so
synthesis/uart_test.srd
synthesis/uart_test.srm
synthesis/uart_test.srr
synthesis/uart_test.srs
synthesis/uart_test.tlg
synthesis/uart_test_sdc.sdc
synthesis/uart_test_syn.prj
viewdraw/vf/project.lst
viewdraw/viewdraw.ini
UART.prj
designer/impl1/uart_test_fp/projectData
designer/impl1/simulation
designer/impl1/uart_test.dtf
designer/impl1/uart_test_fp
designer/impl1
synthesis/backup
synthesis/coreip
synthesis/syntmp
viewdraw/sch
viewdraw/sym
viewdraw/vf
viewdraw/wir
component
constraint
coreconsole
designer
hdl
phy_synthesis
simulation
smartgen
stimulus
synthesis
viewdraw
designer/impl1/uart_test.adb
designer/impl1/uart_test.dtf/verify.log
designer/impl1/uart_test.ide_des
designer/impl1/uart_test.pdb
designer/impl1/uart_test.pdb.depends
designer/impl1/uart_test.tcl
designer/impl1/uart_test_fp/$$FlashPro_FPBBALTLPT1.L$$
designer/impl1/uart_test_fp/projectData/uart_test.pdb
designer/impl1/uart_test_fp/uart_test.log
designer/impl1/uart_test_fp/uart_test.pro
hdl/rec.v
hdl/send.v
hdl/uart_test.v
simulation/modelsim.ini
simulation/modelsim.ini.sav
smartgen/smartgen.aws
synthesis/.recordref
synthesis/backup/uart_test.srr
synthesis/run_options.txt
synthesis/stdout.log
synthesis/syntmp/sap.log
synthesis/syntmp/uart_test.msg
synthesis/syntmp/uart_test.plg
synthesis/syntmp/uart_test_flink.htm
synthesis/syntmp/uart_test_srr.htm
synthesis/syntmp/uart_test_toc.htm
synthesis/traplog.tlg
synthesis/uart_test.areasrr
synthesis/uart_test.edn
synthesis/uart_test.fse
synthesis/uart_test.htm
synthesis/uart_test.map
synthesis/uart_test.sap
synthesis/uart_test.sdf
synthesis/uart_test.so
synthesis/uart_test.srd
synthesis/uart_test.srm
synthesis/uart_test.srr
synthesis/uart_test.srs
synthesis/uart_test.tlg
synthesis/uart_test_sdc.sdc
synthesis/uart_test_syn.prj
viewdraw/vf/project.lst
viewdraw/viewdraw.ini
UART.prj
designer/impl1/uart_test_fp/projectData
designer/impl1/simulation
designer/impl1/uart_test.dtf
designer/impl1/uart_test_fp
designer/impl1
synthesis/backup
synthesis/coreip
synthesis/syntmp
viewdraw/sch
viewdraw/sym
viewdraw/vf
viewdraw/wir
component
constraint
coreconsole
designer
hdl
phy_synthesis
simulation
smartgen
stimulus
synthesis
viewdraw
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.