文件名称:div(FLP).rar
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- 上传时间：2012-09-04
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文件大小：17.93kb
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是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除,Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
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下载文件列表
div(FLP)/conv.vhd
div(FLP)/csa_1bit.vhd
div(FLP)/csa_1weight_odd.vhd
div(FLP)/csa_2weight.vhd
div(FLP)/cube24.vhd
div(FLP)/fa_1bit.vhd
div(FLP)/fpdivider24.vhd
div(FLP)/fpdivider24_v1.vhd
div(FLP)/fpdiv_32.vhd
div(FLP)/index.vhd
div(FLP)/msub24_1bx_shell.vhd
div(FLP)/mult_ax.vhd
div(FLP)/mult_final28.vhd
div(FLP)/mult_sub24_1bx.vhd
div(FLP)/rca_20bit.vhd
div(FLP)/square24.vhd
div(FLP)/sum28.vhd
div(FLP)/sum28_shell.vhd
div(FLP)/table.vhd
div(FLP)/table_shell.vhd
div(FLP)/transcript
div(FLP)/truncate.vhd
div(FLP)/vish_stacktrace.vstf
div(FLP)/words.vhd
div(FLP)
div(FLP)/csa_1bit.vhd
div(FLP)/csa_1weight_odd.vhd
div(FLP)/csa_2weight.vhd
div(FLP)/cube24.vhd
div(FLP)/fa_1bit.vhd
div(FLP)/fpdivider24.vhd
div(FLP)/fpdivider24_v1.vhd
div(FLP)/fpdiv_32.vhd
div(FLP)/index.vhd
div(FLP)/msub24_1bx_shell.vhd
div(FLP)/mult_ax.vhd
div(FLP)/mult_final28.vhd
div(FLP)/mult_sub24_1bx.vhd
div(FLP)/rca_20bit.vhd
div(FLP)/square24.vhd
div(FLP)/sum28.vhd
div(FLP)/sum28_shell.vhd
div(FLP)/table.vhd
div(FLP)/table_shell.vhd
div(FLP)/transcript
div(FLP)/truncate.vhd
div(FLP)/vish_stacktrace.vstf
div(FLP)/words.vhd
div(FLP)
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