文件名称:wb_lpc_latest.tar.gz
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- 上传时间：2012-09-04
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文件大小：401.32kb
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已下载：1次
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介绍说明－－下载内容来自于网络，使用问题请自行百度
Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
None of this has been tested (yet) with a third-party LPC Peripheral or Host.,Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
None of this has been tested (yet) with a third-party LPC Peripheral or Host.
None of this has been tested (yet) with a third-party LPC Peripheral or Host.,Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
None of this has been tested (yet) with a third-party LPC Peripheral or Host.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
./trunk/
./trunk/rtl/
./trunk/rtl/verilog/
./trunk/rtl/verilog/wb_lpc_host.v
./trunk/rtl/verilog/wb_dreq_host.v
./trunk/rtl/verilog/wb_dreq_periph.v
./trunk/rtl/verilog/wb_regfile.v
./trunk/rtl/verilog/wb_lpc_defines.v
./trunk/rtl/verilog/serirq_host.v
./trunk/rtl/verilog/serirq_slave.v
./trunk/rtl/verilog/wb_lpc_periph.v
./trunk/rtl/verilog/serirq_defines.v
./trunk/sim/
./trunk/sim/wb_lpc_sim/
./trunk/sim/wb_lpc_sim/wb_lpc_sim.ise
./trunk/sim/wb_lpc_sim/tb_lpc_top.v
./trunk/sim/serirq_sim/
./trunk/sim/serirq_sim/tb_serirq_top.v
./trunk/sim/serirq_sim/serirq_sim.ise
./trunk/examples/
./trunk/examples/lpc_7seg/
./trunk/examples/lpc_7seg/lpc_7seg.ucf
./trunk/examples/lpc_7seg/disp_dec.vhd
./trunk/examples/lpc_7seg/lpc_7seg.bit
./trunk/examples/lpc_7seg/lpc_7seg.ise
./trunk/examples/lpc_7seg/top_lpc_7seg.v
./trunk/examples/lpc_7seg/wb_7seg.vhd
./trunk/examples/pci_lpc/
./trunk/examples/pci_lpc/pci_lpc.ise
./trunk/examples/pci_lpc/top_pci_lpc_host.v
./trunk/examples/pci_lpc/pci_lpc.ucf
./trunk/examples/pci_lpc/pci_lpc_host.bit
./trunk/examples/README.TXT
./trunk/doc/
./trunk/doc/wb_lpc.pdf
./trunk/doc/src/
./trunk/rtl/
./trunk/rtl/verilog/
./trunk/rtl/verilog/wb_lpc_host.v
./trunk/rtl/verilog/wb_dreq_host.v
./trunk/rtl/verilog/wb_dreq_periph.v
./trunk/rtl/verilog/wb_regfile.v
./trunk/rtl/verilog/wb_lpc_defines.v
./trunk/rtl/verilog/serirq_host.v
./trunk/rtl/verilog/serirq_slave.v
./trunk/rtl/verilog/wb_lpc_periph.v
./trunk/rtl/verilog/serirq_defines.v
./trunk/sim/
./trunk/sim/wb_lpc_sim/
./trunk/sim/wb_lpc_sim/wb_lpc_sim.ise
./trunk/sim/wb_lpc_sim/tb_lpc_top.v
./trunk/sim/serirq_sim/
./trunk/sim/serirq_sim/tb_serirq_top.v
./trunk/sim/serirq_sim/serirq_sim.ise
./trunk/examples/
./trunk/examples/lpc_7seg/
./trunk/examples/lpc_7seg/lpc_7seg.ucf
./trunk/examples/lpc_7seg/disp_dec.vhd
./trunk/examples/lpc_7seg/lpc_7seg.bit
./trunk/examples/lpc_7seg/lpc_7seg.ise
./trunk/examples/lpc_7seg/top_lpc_7seg.v
./trunk/examples/lpc_7seg/wb_7seg.vhd
./trunk/examples/pci_lpc/
./trunk/examples/pci_lpc/pci_lpc.ise
./trunk/examples/pci_lpc/top_pci_lpc_host.v
./trunk/examples/pci_lpc/pci_lpc.ucf
./trunk/examples/pci_lpc/pci_lpc_host.bit
./trunk/examples/README.TXT
./trunk/doc/
./trunk/doc/wb_lpc.pdf
./trunk/doc/src/
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