文件名称:hssdrc_latest.tar.gz
-
所属分类：
- 标签属性：
- 上传时间：2012-09-04
-
文件大小：414.7kb
-
已下载：1次
-
提 供 者：
-
相关连接：无下载说明：别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容来自于网络，使用问题请自行百度
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License,HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License,HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
(系统自动生成,下载前可以参看下载内容)
下载文件列表
./trunk/
./trunk/testbench/
./trunk/testbench/message_class.sv
./trunk/testbench/hssrdc_driver_cbs_class.sv
./trunk/testbench/sdram_interpretator.sv
./trunk/testbench/tb_prog.sv
./trunk/testbench/tb_top.sv
./trunk/testbench/hssrdc_scoreboard_class.sv
./trunk/testbench/hssdrc_driver_class.sv
./trunk/testbench/sdram_transaction_class.sv
./trunk/testbench/sdram_tread_class.sv
./trunk/testbench/hssrdc_bandwidth_monitor_class.sv
./trunk/testbench/sdram_agent_class.sv
./trunk/rtl/
./trunk/rtl/hssdrc_refr_counter.v
./trunk/rtl/hssdrc_init_state.v
./trunk/rtl/hssdrc_arbiter_in.v
./trunk/rtl/hssdrc_data_path.v
./trunk/rtl/hssdrc_decoder.v
./trunk/rtl/hssdrc_arbiter_out.v
./trunk/rtl/hssdrc_mux.v
./trunk/rtl/hssdrc_access_manager.v
./trunk/rtl/hssdrc_addr_path_p1.v
./trunk/rtl/hssdrc_addr_path.v
./trunk/rtl/hssdrc_decoder_state.v
./trunk/rtl/hssdrc_top.v
./trunk/rtl/hssdrc_ba_map.v
./trunk/rtl/hssdrc_data_path_p1.v
./trunk/sim/
./trunk/sim/compile.do
./trunk/sim/sim.do
./trunk/core/
./trunk/core/test.v
./trunk/core/mt48lc2m32b2.v
./trunk/include/
./trunk/include/hssdrc_timing.vh
./trunk/include/hssdrc_timescale.vh
./trunk/include/hssdrc_define.vh
./trunk/include/hssdrc_tb_sys_if.vh
./trunk/include/tb_define.svh
./trunk/readme.txt
./trunk/doc/
./trunk/doc/hssdrc_design_document_rev10.odt
./trunk/doc/hssdrc_design_document.pdf
./trunk/testbench/
./trunk/testbench/message_class.sv
./trunk/testbench/hssrdc_driver_cbs_class.sv
./trunk/testbench/sdram_interpretator.sv
./trunk/testbench/tb_prog.sv
./trunk/testbench/tb_top.sv
./trunk/testbench/hssrdc_scoreboard_class.sv
./trunk/testbench/hssdrc_driver_class.sv
./trunk/testbench/sdram_transaction_class.sv
./trunk/testbench/sdram_tread_class.sv
./trunk/testbench/hssrdc_bandwidth_monitor_class.sv
./trunk/testbench/sdram_agent_class.sv
./trunk/rtl/
./trunk/rtl/hssdrc_refr_counter.v
./trunk/rtl/hssdrc_init_state.v
./trunk/rtl/hssdrc_arbiter_in.v
./trunk/rtl/hssdrc_data_path.v
./trunk/rtl/hssdrc_decoder.v
./trunk/rtl/hssdrc_arbiter_out.v
./trunk/rtl/hssdrc_mux.v
./trunk/rtl/hssdrc_access_manager.v
./trunk/rtl/hssdrc_addr_path_p1.v
./trunk/rtl/hssdrc_addr_path.v
./trunk/rtl/hssdrc_decoder_state.v
./trunk/rtl/hssdrc_top.v
./trunk/rtl/hssdrc_ba_map.v
./trunk/rtl/hssdrc_data_path_p1.v
./trunk/sim/
./trunk/sim/compile.do
./trunk/sim/sim.do
./trunk/core/
./trunk/core/test.v
./trunk/core/mt48lc2m32b2.v
./trunk/include/
./trunk/include/hssdrc_timing.vh
./trunk/include/hssdrc_timescale.vh
./trunk/include/hssdrc_define.vh
./trunk/include/hssdrc_tb_sys_if.vh
./trunk/include/tb_define.svh
./trunk/readme.txt
./trunk/doc/
./trunk/doc/hssdrc_design_document_rev10.odt
./trunk/doc/hssdrc_design_document.pdf
本网站为编程资源及源代码搜集、介绍的搜索网站，版权归原作者所有！ 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.