文件名称:sim.rar
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- 上传时间:2012-09-04
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文件大小:33.35kb
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通用的循环码编码器和(7,4)循环码译码器。采用VERILOG HDL编写,通过硬件验证。需使用modelsim 5.6仿真,Common cyclic code encoder and (7,4) cyclic code decoder. VERILOG HDL preparation used by the hardware verification. Need to use simulation modelsim 5.6
相关搜索: 循环码
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下载文件列表
sim/bm/bm.v
sim/bm/t_bm.v
sim/bm/vsim.wlf
sim/bm/work/bm/verilog.asm
sim/bm/work/bm/_primary.dat
sim/bm/work/bm/_primary.vhd
sim/bm/work/t_bm/verilog.asm
sim/bm/work/t_bm/_primary.dat
sim/bm/work/t_bm/_primary.vhd
sim/bm/work/_info
sim/bm/work.cr.mti
sim/bm/work.mpf
sim/ym/alpha.cr.mti
sim/ym/alpha.mpf
sim/ym/transcript
sim/ym/vsim.wlf
sim/ym/work/ym/verilog.asm
sim/ym/work/ym/_primary.dat
sim/ym/work/ym/_primary.vhd
sim/ym/work/ym_t/verilog.asm
sim/ym/work/ym_t/_primary.dat
sim/ym/work/ym_t/_primary.vhd
sim/ym/work/_info
sim/ym/work.cr.mti
sim/ym/work.mpf
sim/ym/ym.v
sim/ym/ym_t.v
sim/bm/work/bm
sim/bm/work/t_bm
sim/ym/work/ym
sim/ym/work/ym_t
sim/bm/work
sim/ym/work
sim/bm
sim/ym
sim
sim/bm/t_bm.v
sim/bm/vsim.wlf
sim/bm/work/bm/verilog.asm
sim/bm/work/bm/_primary.dat
sim/bm/work/bm/_primary.vhd
sim/bm/work/t_bm/verilog.asm
sim/bm/work/t_bm/_primary.dat
sim/bm/work/t_bm/_primary.vhd
sim/bm/work/_info
sim/bm/work.cr.mti
sim/bm/work.mpf
sim/ym/alpha.cr.mti
sim/ym/alpha.mpf
sim/ym/transcript
sim/ym/vsim.wlf
sim/ym/work/ym/verilog.asm
sim/ym/work/ym/_primary.dat
sim/ym/work/ym/_primary.vhd
sim/ym/work/ym_t/verilog.asm
sim/ym/work/ym_t/_primary.dat
sim/ym/work/ym_t/_primary.vhd
sim/ym/work/_info
sim/ym/work.cr.mti
sim/ym/work.mpf
sim/ym/ym.v
sim/ym/ym_t.v
sim/bm/work/bm
sim/bm/work/t_bm
sim/ym/work/ym
sim/ym/work/ym_t
sim/bm/work
sim/ym/work
sim/bm
sim/ym
sim
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