文件名称:c822.rar
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关于FPGA的一个设计,用FPGA来实现数字示波器,采样时钟为250M,On a FPGA design, FPGA to realize digital oscilloscope, the sampling clock for the 250M
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下载文件列表
c82/altpll0.bsf
c82/altpll0.tdf
c82/altpll0_inst.tdf
c82/altpll0_wave0.jpg
c82/altpll0_waveforms.html
c82/db/altsyncram_95b1.tdf
c82/db/altsyncram_fsb2.tdf
c82/db/altsyncram_ric1.tdf
c82/db/cmpr_nth.tdf
c82/db/cntr_6sb.tdf
c82/db/cntr_7jc.tdf
c82/db/cntr_esa.tdf
c82/db/cntr_igb.tdf
c82/db/cntr_smd.tdf
c82/db/decode_rpe.tdf
c82/db/sdram.(0).cnf.cdb
c82/db/sdram.(0).cnf.hdb
c82/db/sdram.(1).cnf.cdb
c82/db/sdram.(1).cnf.hdb
c82/db/sdram.(10).cnf.cdb
c82/db/sdram.(10).cnf.hdb
c82/db/sdram.(11).cnf.cdb
c82/db/sdram.(11).cnf.hdb
c82/db/sdram.(12).cnf.cdb
c82/db/sdram.(12).cnf.hdb
c82/db/sdram.(2).cnf.cdb
c82/db/sdram.(2).cnf.hdb
c82/db/sdram.(3).cnf.cdb
c82/db/sdram.(3).cnf.hdb
c82/db/sdram.(4).cnf.cdb
c82/db/sdram.(4).cnf.hdb
c82/db/sdram.(5).cnf.cdb
c82/db/sdram.(5).cnf.hdb
c82/db/sdram.(6).cnf.cdb
c82/db/sdram.(6).cnf.hdb
c82/db/sdram.(7).cnf.cdb
c82/db/sdram.(7).cnf.hdb
c82/db/sdram.(8).cnf.cdb
c82/db/sdram.(8).cnf.hdb
c82/db/sdram.(9).cnf.cdb
c82/db/sdram.(9).cnf.hdb
c82/db/sdram.asm.qmsg
c82/db/sdram.asm_labs.ddb
c82/db/sdram.cbx.xml
c82/db/sdram.cmp.cdb
c82/db/sdram.cmp.hdb
c82/db/sdram.cmp.logdb
c82/db/sdram.cmp.qrpt
c82/db/sdram.cmp.rdb
c82/db/sdram.cmp.tdb
c82/db/sdram.cmp0.ddb
c82/db/sdram.cmp2.ddb
c82/db/sdram.dbp
c82/db/sdram.db_info
c82/db/sdram.eco.cdb
c82/db/sdram.fit.qmsg
c82/db/sdram.hier_info
c82/db/sdram.hif
c82/db/sdram.map.cdb
c82/db/sdram.map.hdb
c82/db/sdram.map.logdb
c82/db/sdram.map.qmsg
c82/db/sdram.pre_map.cdb
c82/db/sdram.pre_map.hdb
c82/db/sdram.psp
c82/db/sdram.rpp.qmsg
c82/db/sdram.rtlv.hdb
c82/db/sdram.rtlv_sg.cdb
c82/db/sdram.rtlv_sg_swap.cdb
c82/db/sdram.sgate.rvd
c82/db/sdram.sgate_sm.rvd
c82/db/sdram.sgdiff.cdb
c82/db/sdram.sgdiff.hdb
c82/db/sdram.signalprobe.cdb
c82/db/sdram.sld_design_entry.sci
c82/db/sdram.sld_design_entry_dsc.sci
c82/db/sdram.smp_dump.txt
c82/db/sdram.syn_hier_info
c82/db/sdram.tan.qmsg
c82/divclk.bsf
c82/divclk.v
c82/equ_sam.bsf
c82/equ_sam.v
c82/lpm_or0.bsf
c82/lpm_or0.tdf
c82/lpm_or0_inst.tdf
c82/lpm_or1.bsf
c82/lpm_or1.vhd
c82/lpm_ram_dp0.bsf
c82/lpm_ram_dp0.v
c82/lpm_ram_dp0_bb.v
c82/pre_clk.bsf
c82/pre_clk.v
c82/rd_adrcount.bsf
c82/rd_adrcount.v
c82/rd_ram.bsf
c82/rd_ram.v
c82/sdram.asm.rpt
c82/sdram.bdf
c82/sdram.cdf
c82/sdram.done
c82/sdram.dpf
c82/sdram.fit.eqn
c82/sdram.fit.rpt
c82/sdram.fit.summary
c82/sdram.flow.rpt
c82/sdram.jic
c82/sdram.map
c82/sdram.map.eqn
c82/sdram.map.rpt
c82/sdram.map.summary
c82/sdram.pin
c82/sdram.pof
c82/sdram.qpf
c82/sdram.qsf
c82/sdram.qws
c82/sdram.sof
c82/sdram.tan.rpt
c82/sdram.tan.summary
c82/start_FPGA.v
c82/triangle_wave.bsf
c82/triangle_wave.v
c82/wr_ram.bsf
c82/wr_ram.v
c82/db
c82
c82/altpll0.tdf
c82/altpll0_inst.tdf
c82/altpll0_wave0.jpg
c82/altpll0_waveforms.html
c82/db/altsyncram_95b1.tdf
c82/db/altsyncram_fsb2.tdf
c82/db/altsyncram_ric1.tdf
c82/db/cmpr_nth.tdf
c82/db/cntr_6sb.tdf
c82/db/cntr_7jc.tdf
c82/db/cntr_esa.tdf
c82/db/cntr_igb.tdf
c82/db/cntr_smd.tdf
c82/db/decode_rpe.tdf
c82/db/sdram.(0).cnf.cdb
c82/db/sdram.(0).cnf.hdb
c82/db/sdram.(1).cnf.cdb
c82/db/sdram.(1).cnf.hdb
c82/db/sdram.(10).cnf.cdb
c82/db/sdram.(10).cnf.hdb
c82/db/sdram.(11).cnf.cdb
c82/db/sdram.(11).cnf.hdb
c82/db/sdram.(12).cnf.cdb
c82/db/sdram.(12).cnf.hdb
c82/db/sdram.(2).cnf.cdb
c82/db/sdram.(2).cnf.hdb
c82/db/sdram.(3).cnf.cdb
c82/db/sdram.(3).cnf.hdb
c82/db/sdram.(4).cnf.cdb
c82/db/sdram.(4).cnf.hdb
c82/db/sdram.(5).cnf.cdb
c82/db/sdram.(5).cnf.hdb
c82/db/sdram.(6).cnf.cdb
c82/db/sdram.(6).cnf.hdb
c82/db/sdram.(7).cnf.cdb
c82/db/sdram.(7).cnf.hdb
c82/db/sdram.(8).cnf.cdb
c82/db/sdram.(8).cnf.hdb
c82/db/sdram.(9).cnf.cdb
c82/db/sdram.(9).cnf.hdb
c82/db/sdram.asm.qmsg
c82/db/sdram.asm_labs.ddb
c82/db/sdram.cbx.xml
c82/db/sdram.cmp.cdb
c82/db/sdram.cmp.hdb
c82/db/sdram.cmp.logdb
c82/db/sdram.cmp.qrpt
c82/db/sdram.cmp.rdb
c82/db/sdram.cmp.tdb
c82/db/sdram.cmp0.ddb
c82/db/sdram.cmp2.ddb
c82/db/sdram.dbp
c82/db/sdram.db_info
c82/db/sdram.eco.cdb
c82/db/sdram.fit.qmsg
c82/db/sdram.hier_info
c82/db/sdram.hif
c82/db/sdram.map.cdb
c82/db/sdram.map.hdb
c82/db/sdram.map.logdb
c82/db/sdram.map.qmsg
c82/db/sdram.pre_map.cdb
c82/db/sdram.pre_map.hdb
c82/db/sdram.psp
c82/db/sdram.rpp.qmsg
c82/db/sdram.rtlv.hdb
c82/db/sdram.rtlv_sg.cdb
c82/db/sdram.rtlv_sg_swap.cdb
c82/db/sdram.sgate.rvd
c82/db/sdram.sgate_sm.rvd
c82/db/sdram.sgdiff.cdb
c82/db/sdram.sgdiff.hdb
c82/db/sdram.signalprobe.cdb
c82/db/sdram.sld_design_entry.sci
c82/db/sdram.sld_design_entry_dsc.sci
c82/db/sdram.smp_dump.txt
c82/db/sdram.syn_hier_info
c82/db/sdram.tan.qmsg
c82/divclk.bsf
c82/divclk.v
c82/equ_sam.bsf
c82/equ_sam.v
c82/lpm_or0.bsf
c82/lpm_or0.tdf
c82/lpm_or0_inst.tdf
c82/lpm_or1.bsf
c82/lpm_or1.vhd
c82/lpm_ram_dp0.bsf
c82/lpm_ram_dp0.v
c82/lpm_ram_dp0_bb.v
c82/pre_clk.bsf
c82/pre_clk.v
c82/rd_adrcount.bsf
c82/rd_adrcount.v
c82/rd_ram.bsf
c82/rd_ram.v
c82/sdram.asm.rpt
c82/sdram.bdf
c82/sdram.cdf
c82/sdram.done
c82/sdram.dpf
c82/sdram.fit.eqn
c82/sdram.fit.rpt
c82/sdram.fit.summary
c82/sdram.flow.rpt
c82/sdram.jic
c82/sdram.map
c82/sdram.map.eqn
c82/sdram.map.rpt
c82/sdram.map.summary
c82/sdram.pin
c82/sdram.pof
c82/sdram.qpf
c82/sdram.qsf
c82/sdram.qws
c82/sdram.sof
c82/sdram.tan.rpt
c82/sdram.tan.summary
c82/start_FPGA.v
c82/triangle_wave.bsf
c82/triangle_wave.v
c82/wr_ram.bsf
c82/wr_ram.v
c82/db
c82
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