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文件名称:xge_mac_latest.tar.gz

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    2012-09-04
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Language - Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae. ,Language- Verilog. The 10GE MAC Core implements the Media Access Control functions for 10Gbps operation as defined in IEEE Std 802.3ae.
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下载文件列表

./
./xge_mac/
./xge_mac/tags/
./xge_mac/tags/initial/
./xge_mac/tags/initial/tbench/
./xge_mac/tags/initial/tbench/systemc/
./xge_mac/tags/initial/tbench/systemc/sc_cpu_if.cpp
./xge_mac/tags/initial/tbench/systemc/sc_testbench.cpp
./xge_mac/tags/initial/tbench/systemc/sc_testbench.h
./xge_mac/tags/initial/tbench/systemc/sc_testcases.cpp
./xge_mac/tags/initial/tbench/systemc/sc_xgmii_if.cpp
./xge_mac/tags/initial/tbench/systemc/sc_pkt_if.cpp
./xge_mac/tags/initial/tbench/systemc/sc_testcases.h
./xge_mac/tags/initial/tbench/systemc/sc_cpu_if.h
./xge_mac/tags/initial/tbench/systemc/sc_pkt_generator.cpp
./xge_mac/tags/initial/tbench/systemc/crc.h
./xge_mac/tags/initial/tbench/systemc/sc_scoreboard.h
./xge_mac/tags/initial/tbench/systemc/sc_packet.h
./xge_mac/tags/initial/tbench/systemc/sc_main.cpp
./xge_mac/tags/initial/tbench/systemc/sc_pkt_generator.h
./xge_mac/tags/initial/tbench/systemc/crc.cpp
./xge_mac/tags/initial/tbench/systemc/sc_xgmii_if.h
./xge_mac/tags/initial/tbench/systemc/sc_packet.cpp
./xge_mac/tags/initial/tbench/systemc/sc_scoreboard.cpp
./xge_mac/tags/initial/tbench/systemc/sc_pkt_if.h
./xge_mac/tags/initial/tbench/verilog/
./xge_mac/tags/initial/tbench/verilog/tb_xge_mac.v
./xge_mac/tags/initial/tbench/verilog/packets_tx.txt
./xge_mac/tags/initial/README.TXT
./xge_mac/tags/initial/doc/
./xge_mac/tags/initial/doc/xge_mac_spec.odt
./xge_mac/tags/initial/rtl/
./xge_mac/tags/initial/rtl/include/
./xge_mac/tags/initial/rtl/include/utils.v
./xge_mac/tags/initial/rtl/include/defines.v
./xge_mac/tags/initial/rtl/include/timescale.v
./xge_mac/tags/initial/rtl/include/CRC32_D64.v
./xge_mac/tags/initial/rtl/include/CRC32_D8.v
./xge_mac/tags/initial/rtl/verilog/
./xge_mac/tags/initial/rtl/verilog/xge_mac.v
./xge_mac/tags/initial/rtl/verilog/tx_dequeue.v
./xge_mac/tags/initial/rtl/verilog/generic_fifo.v
./xge_mac/tags/initial/rtl/verilog/generic_fifo_ctrl.v
./xge_mac/tags/initial/rtl/verilog/tx_enqueue.v
./xge_mac/tags/initial/rtl/verilog/meta_sync_single.v
./xge_mac/tags/initial/rtl/verilog/generic_mem_medium.v
./xge_mac/tags/initial/rtl/verilog/rx_data_fifo.v
./xge_mac/tags/initial/rtl/verilog/wishbone_if.v
./xge_mac/tags/initial/rtl/verilog/tx_hold_fifo.v
./xge_mac/tags/initial/rtl/verilog/rx_dequeue.v
./xge_mac/tags/initial/rtl/verilog/sync_clk_xgmii_tx.v
./xge_mac/tags/initial/rtl/verilog/rx_hold_fifo.v
./xge_mac/tags/initial/rtl/verilog/tx_data_fifo.v
./xge_mac/tags/initial/rtl/verilog/rx_enqueue.v
./xge_mac/tags/initial/rtl/verilog/sync_clk_core.v
./xge_mac/tags/initial/rtl/verilog/meta_sync.v
./xge_mac/tags/initial/rtl/verilog/generic_mem_small.v
./xge_mac/tags/initial/rtl/verilog/sync_clk_wb.v
./xge_mac/tags/initial/rtl/verilog/fault_sm.v
./xge_mac/tags/initial/rtl/custom.el
./xge_mac/tags/initial/rtl/auto_verilog.sh
./xge_mac/tags/initial/sim/
./xge_mac/tags/initial/sim/systemc/
./xge_mac/tags/initial/sim/systemc/compile.sh
./xge_mac/tags/initial/sim/systemc/sc.mk
./xge_mac/tags/initial/sim/systemc/run.sh
./xge_mac/tags/initial/sim/systemc/verilator.cmd
./xge_mac/tags/initial/sim/verilog/
./xge_mac/tags/initial/sim/verilog/sim.do
./xge_mac/branches/
./xge_mac/web_uploads/
./xge_mac/trunk/
./xge_mac/trunk/tbench/
./xge_mac/trunk/tbench/systemc/
./xge_mac/trunk/tbench/systemc/sc_cpu_if.cpp
./xge_mac/trunk/tbench/systemc/sc_testbench.cpp
./xge_mac/trunk/tbench/systemc/sc_testbench.h
./xge_mac/trunk/tbench/systemc/sc_testcases.cpp
./xge_mac/trunk/tbench/systemc/sc_xgmii_if.cpp
./xge_mac/trunk/tbench/systemc/sc_pkt_if.cpp
./xge_mac/trunk/tbench/systemc/sc_testcases.h
./xge_mac/trunk/tbench/systemc/sc_cpu_if.h
./xge_mac/trunk/tbench/systemc/sc_pkt_generator.cpp
./xge_mac/trunk/tbench/systemc/crc.h
./xge_mac/trunk/tbench/systemc/sc_scoreboard.h
./xge_mac/trunk/tbench/systemc/sc_packet.h
./xge_mac/trunk/tbench/systemc/sc_main.cpp
./xge_mac/trunk/tbench/systemc/sc_pkt_generator.h
./xge_mac/trunk/tbench/systemc/crc.cpp
./xge_mac/trunk/tbench/systemc/sc_xgmii_if.h
./xge_mac/trunk/tbench/systemc/sc_packet.cpp
./xge_mac/trunk/tbench/systemc/sc_scoreboard.cpp
./xge_mac/trunk/tbench/systemc/sc_pkt_if.h
./xge_mac/trunk/tbench/verilog/
./xge_mac/trunk/tbench/verilog/tb_xge_mac.v
./xge_mac/trunk/tbench/verilog/packets_tx.txt
./xge_mac/trunk/README.TXT
./xge_mac/trunk/doc/
./xge_mac/trunk/doc/xge_mac_spec.odt
./xge_mac/trunk/doc/drawings.odg
./xge_mac/trunk/doc/xge_mac_spec.pdf
./xge_mac/trunk/rtl/
./xge_mac/trunk/rtl/include/
./xge_mac/trunk/rtl/include/utils.v
./xge_mac/trunk/rtl/include/defines.v
./xge_mac/trunk/rtl/include/timescale.v
./xge_mac/trunk/rtl/include/CRC32_D64.v
./xge_mac/trunk/rtl/include/CRC32_D8.v
./xge_mac/trunk/rtl/verilog/
./xge_mac/trunk/rtl/verilog/xge_mac.v
./xge_mac/trunk/rtl/verilog/tx_dequeue.v
./xge_mac/trunk/rtl/verilog/generic_fifo.v
./xge_mac/trunk/rtl/verilog/generic_fifo_ctrl.v
./xge_mac/trunk/rtl/verilog/tx_enqueue.v
./xge_mac/trunk/rtl/verilog/meta_sync_single.v
./xge_mac/trunk/rtl/verilog/generic_mem_medium.v
./xge_mac/trunk/rtl/verilog/rx_data_fifo.v
./xge_mac/trunk/rtl/verilog/wishbone_if.v
./xge_mac/trunk/rtl/verilog/tx_hold_fifo.v
./xge_mac/trunk/rtl/verilog/rx_dequeue.v
./xge_mac/trunk/rtl

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