文件名称:SCIA模块的发送和接收采用中断方式实现
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- 上传时间:2012-09-04
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文件大小:337.52kb
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本实验中SCIA模块的发送和接收采用中断方式实现,空闲线模式波特率为19200,
* 通信数据格式为1位停止位,8位数据位,无校验位-This experiment SCIA transmit and receive modules achieved by interrupt, idle line mode the baud rate is 19200,* communication data format is 1 stop bit, 8 data bits, no parity
* 通信数据格式为1位停止位,8位数据位,无校验位-This experiment SCIA transmit and receive modules achieved by interrupt, idle line mode the baud rate is 19200,* communication data format is 1 stop bit, 8 data bits, no parity
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下载文件列表
07_Sci02/Sci02实验说明.txt
07_Sci02/Sci02/DSP28_Adc.h
07_Sci02/Sci02/DSP28_CpuTimers.h
07_Sci02/Sci02/DSP28_DefaultIsr.c
07_Sci02/Sci02/DSP28_DefaultIsr.h
07_Sci02/Sci02/DSP28_DevEmu.h
07_Sci02/Sci02/DSP28_Device.h
07_Sci02/Sci02/DSP28_ECan.h
07_Sci02/Sci02/DSP28_Ev.h
07_Sci02/Sci02/DSP28_GlobalPrototypes.h
07_Sci02/Sci02/DSP28_GlobalVariable.h
07_Sci02/Sci02/DSP28_GlobalVariableDefs.c
07_Sci02/Sci02/DSP28_Gpio.c
07_Sci02/Sci02/DSP28_Gpio.h
07_Sci02/Sci02/DSP28_InitPeripherals.c
07_Sci02/Sci02/DSP28_Mcbsp.h
07_Sci02/Sci02/DSP28_PieCtrl.c
07_Sci02/Sci02/DSP28_PieCtrl.h
07_Sci02/Sci02/DSP28_PieVect.c
07_Sci02/Sci02/DSP28_PieVect.h
07_Sci02/Sci02/DSP28_Sci.c
07_Sci02/Sci02/DSP28_Sci.h
07_Sci02/Sci02/DSP28_Spi.h
07_Sci02/Sci02/DSP28_SysCtrl.c
07_Sci02/Sci02/DSP28_SysCtrl.h
07_Sci02/Sci02/DSP28_XIntrupt.h
07_Sci02/Sci02/DSP28_Xintf.h
07_Sci02/Sci02/Debug.lkf
07_Sci02/Sci02/Debug.lkv
07_Sci02/Sci02/SRAM.cmd
07_Sci02/Sci02/Sci01.c
07_Sci02/Sci02/Sci02.paf
07_Sci02/Sci02/Sci02.paf2
07_Sci02/Sci02/Sci02.pjt
07_Sci02/Sci02/Sci02.sbl
07_Sci02/Sci02/cc_build_Debug.log
07_Sci02/Sci02/Sci02.CS_/FILE.CDX
07_Sci02/Sci02/Sci02.CS_/FILE.DBF
07_Sci02/Sci02/Sci02.CS_/FILE.FPT
07_Sci02/Sci02/Sci02.CS_/SYMBOL.CDX
07_Sci02/Sci02/Sci02.CS_/SYMBOL.DBF
07_Sci02/Sci02/Sci02.CS_/SYMBOL.FPT
07_Sci02/Sci02/Debug/DSP28_DefaultIsr.obj
07_Sci02/Sci02/Debug/DSP28_GlobalVariableDefs.obj
07_Sci02/Sci02/Debug/DSP28_Gpio.obj
07_Sci02/Sci02/Debug/DSP28_InitPeripherals.obj
07_Sci02/Sci02/Debug/DSP28_PieCtrl.obj
07_Sci02/Sci02/Debug/DSP28_PieVect.obj
07_Sci02/Sci02/Debug/DSP28_Sci.obj
07_Sci02/Sci02/Debug/DSP28_SysCtrl.obj
07_Sci02/Sci02/Debug/Sci01.obj
07_Sci02/Sci02/Debug/Sci02.map
07_Sci02/Sci02/Debug/Sci02.out
07_Sci02/Sci02/Sci02.CS_
07_Sci02/Sci02/Debug
07_Sci02/Sci02
07_Sci02
07_Sci02/Sci02/DSP28_Adc.h
07_Sci02/Sci02/DSP28_CpuTimers.h
07_Sci02/Sci02/DSP28_DefaultIsr.c
07_Sci02/Sci02/DSP28_DefaultIsr.h
07_Sci02/Sci02/DSP28_DevEmu.h
07_Sci02/Sci02/DSP28_Device.h
07_Sci02/Sci02/DSP28_ECan.h
07_Sci02/Sci02/DSP28_Ev.h
07_Sci02/Sci02/DSP28_GlobalPrototypes.h
07_Sci02/Sci02/DSP28_GlobalVariable.h
07_Sci02/Sci02/DSP28_GlobalVariableDefs.c
07_Sci02/Sci02/DSP28_Gpio.c
07_Sci02/Sci02/DSP28_Gpio.h
07_Sci02/Sci02/DSP28_InitPeripherals.c
07_Sci02/Sci02/DSP28_Mcbsp.h
07_Sci02/Sci02/DSP28_PieCtrl.c
07_Sci02/Sci02/DSP28_PieCtrl.h
07_Sci02/Sci02/DSP28_PieVect.c
07_Sci02/Sci02/DSP28_PieVect.h
07_Sci02/Sci02/DSP28_Sci.c
07_Sci02/Sci02/DSP28_Sci.h
07_Sci02/Sci02/DSP28_Spi.h
07_Sci02/Sci02/DSP28_SysCtrl.c
07_Sci02/Sci02/DSP28_SysCtrl.h
07_Sci02/Sci02/DSP28_XIntrupt.h
07_Sci02/Sci02/DSP28_Xintf.h
07_Sci02/Sci02/Debug.lkf
07_Sci02/Sci02/Debug.lkv
07_Sci02/Sci02/SRAM.cmd
07_Sci02/Sci02/Sci01.c
07_Sci02/Sci02/Sci02.paf
07_Sci02/Sci02/Sci02.paf2
07_Sci02/Sci02/Sci02.pjt
07_Sci02/Sci02/Sci02.sbl
07_Sci02/Sci02/cc_build_Debug.log
07_Sci02/Sci02/Sci02.CS_/FILE.CDX
07_Sci02/Sci02/Sci02.CS_/FILE.DBF
07_Sci02/Sci02/Sci02.CS_/FILE.FPT
07_Sci02/Sci02/Sci02.CS_/SYMBOL.CDX
07_Sci02/Sci02/Sci02.CS_/SYMBOL.DBF
07_Sci02/Sci02/Sci02.CS_/SYMBOL.FPT
07_Sci02/Sci02/Debug/DSP28_DefaultIsr.obj
07_Sci02/Sci02/Debug/DSP28_GlobalVariableDefs.obj
07_Sci02/Sci02/Debug/DSP28_Gpio.obj
07_Sci02/Sci02/Debug/DSP28_InitPeripherals.obj
07_Sci02/Sci02/Debug/DSP28_PieCtrl.obj
07_Sci02/Sci02/Debug/DSP28_PieVect.obj
07_Sci02/Sci02/Debug/DSP28_Sci.obj
07_Sci02/Sci02/Debug/DSP28_SysCtrl.obj
07_Sci02/Sci02/Debug/Sci01.obj
07_Sci02/Sci02/Debug/Sci02.map
07_Sci02/Sci02/Debug/Sci02.out
07_Sci02/Sci02/Sci02.CS_
07_Sci02/Sci02/Debug
07_Sci02/Sci02
07_Sci02
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