文件名称:dlx_verilog.rar
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这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! That can be downloaded to the FPGA to run commands, instructions can be defined as needed, but also the compiler and the corresponding use, where to learn lines and Verilog friends sharing.
相关搜索： DLX_veril
DLX
pipeline
processor verilog code
流水线
vhdl pipeline
dlx vhdl
verilog
verilog coding for rom
(系统自动生成,下载前可以参看下载内容)
下载文件列表
memaccess.v
RAM.v
test_dlx.v
wirteback.v
dlxpipeline.v
instdecode.v
instexec.v
instfetch.v
RAM.v
test_dlx.v
wirteback.v
dlxpipeline.v
instdecode.v
instexec.v
instfetch.v
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