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文件名称:counter.rar

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    2012-09-04
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    3.73mb
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初学者学习modelsim的好例子,基于Verilog的计数器,带测试源码,在quartus2运行。,Modelsim beginners to learn a good example of Verilog based on the counter, with the test source code, running in quartus2.
相关搜索: modelsim VHDL count

(系统自动生成,下载前可以参看下载内容)

下载文件列表

counter/counter.done
counter/counter.fit.smsg
counter/counter.fit.summary
counter/counter.map.summary
counter/counter.pin
counter/counter.pof
counter/counter.qpf
counter/counter.qsf
counter/counter.sof
counter/counter.tan.summary
counter/counter.v
counter/counter_nativelink_simulation.rpt
counter/counter_tb.v
counter/db/counter.(0).cnf.cdb
counter/db/counter.(0).cnf.hdb
counter/db/counter.cmp.rdb
counter/db/counter.cbx.xml
counter/db/counter.cmp.tdb
counter/db/counter.tan.qmsg
counter/db/counter.cmp.bpm
counter/db/counter.cmp.ecobp
counter/db/counter.cmp.kpt
counter/db/counter.tis_db_list.ddb
counter/db/prev_cmp_counter.qmsg
counter/db/counter.asm.qmsg
counter/db/counter.eda.qmsg
counter/db/counter.cmp_merge.kpt
counter/db/counter.db_info
counter/db/counter.sld_design_entry.sci
counter/db/counter.eco.cdb
counter/db/counter.hier_info
counter/db/counter.hif
counter/db/counter.cmp0.ddb
counter/db/counter.cmp.cdb
counter/db/counter.map.ecobp
counter/db/counter.cmp.hdb
counter/db/counter.map.kpt
counter/db/counter.(1).cnf.cdb
counter/db/counter.map_bb.hdbx
counter/db/counter.psp
counter/db/counter.(1).cnf.hdb
counter/db/counter.syn_hier_info
counter/db/counter.tmw_info
counter/db/prev_cmp_counter.map.qmsg
counter/db/prev_cmp_counter.fit.qmsg
counter/db/prev_cmp_counter.asm.qmsg
counter/db/prev_cmp_counter.tan.qmsg
counter/db/prev_cmp_counter.eda.qmsg
counter/db/counter.map.qmsg
counter/db/counter.rtlv_sg.cdb
counter/db/counter.rtlv.hdb
counter/db/counter.rtlv_sg_swap.cdb
counter/db/counter.pre_map.hdb
counter/db/counter.pre_map.cdb
counter/db/counter.map_bb.logdb
counter/db/counter.sgdiff.cdb
counter/db/counter.sgdiff.hdb
counter/db/counter.sld_design_entry_dsc.sci
counter/db/counter.map_bb.cdb
counter/db/counter.map_bb.hdb
counter/db/counter.map.cdb
counter/db/counter.map.hdb
counter/db/counter.map.logdb
counter/db/counter.map.bpm
counter/db/counter.fit.qmsg
counter/db/counter.cmp.logdb
counter/incremental_db/README
counter/incremental_db/compiled_partitions/counter.root_partition.cmp.atm
counter/incremental_db/compiled_partitions/counter.root_partition.cmp.hdbx
counter/incremental_db/compiled_partitions/counter.root_partition.cmp.kpt
counter/incremental_db/compiled_partitions/counter.root_partition.cmp.logdb
counter/incremental_db/compiled_partitions/counter.root_partition.cmp.rcf
counter/incremental_db/compiled_partitions/counter.root_partition.map.atm
counter/incremental_db/compiled_partitions/counter.root_partition.map.hdbx
counter/incremental_db/compiled_partitions/counter.root_partition.map.kpt
counter/incremental_db/compiled_partitions/counter.root_partition.map.dpi
counter/incremental_db/compiled_partitions/counter.root_partition.cmp.dfp
counter/simulation/modelsim/counter.vo
counter/simulation/modelsim/counter_modelsim.xrf
counter/simulation/modelsim/counter_v.sdo
counter/simulation/modelsim/counter_run_msim_rtl_verilog.do
counter/simulation/modelsim/vsim.wlf
counter/simulation/modelsim/counter_run_msim_gate_verilog.do
counter/simulation/modelsim/counter_run_msim_rtl_verilog.do.bak1
counter/simulation/modelsim/counter_run_msim_rtl_verilog.do.bak2
counter/simulation/modelsim/counter_run_msim_rtl_verilog.do.bak3
counter/simulation/modelsim/counter_run_msim_rtl_verilog.do.bak4
counter/simulation/modelsim/counter_run_msim_rtl_verilog.do.bak5
counter/simulation/modelsim/counter_run_msim_rtl_verilog.do.bak6
counter/simulation/modelsim/counter_run_msim_rtl_verilog.do.bak7
counter/simulation/modelsim/counter_run_msim_rtl_verilog.do.bak8
counter/simulation/modelsim/counter_run_msim_rtl_verilog.do.bak9
counter/simulation/modelsim/counter_run_msim_gate_verilog.do.bak1
counter/simulation/modelsim/counter_run_msim_gate_verilog.do.bak2
counter/simulation/modelsim/counter_run_msim_gate_verilog.do.bak3
counter/simulation/modelsim/counter_run_msim_gate_verilog.do.bak4
counter/simulation/modelsim/rtl_work/_info
counter/simulation/modelsim/rtl_work/counter/_primary.vhd
counter/simulation/modelsim/rtl_work/counter/verilog.asm
counter/simulation/modelsim/rtl_work/counter/_primary.dat
counter/simulation/modelsim/verilog_libs/cyclone_ver/_info
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_asmiblock/_primary.vhd
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_asmiblock/verilog.asm
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_asmiblock/_primary.dat
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_io/_primary.vhd
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_io/verilog.asm
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_io/_primary.dat
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_asynch_io/_primary.vhd
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_asynch_io/verilog.asm
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_asynch_io/_primary.dat
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_routing_wire/_primary.vhd
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_routing_wire/verilog.asm
counter/simulation/modelsim/verilog_libs/cyclone_ver/cyclone_routing_wire/_primary.dat
counter/simulation/modelsi

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