文件名称:EasyFPGA030.part1.rar
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- 上传时间:2012-09-04
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文件大小:8.42mb
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周立功 EasyFPGA030 开发板光盘1,,EasyFPGA030 development board CD-ROM 1
相关搜索: EasyFPGA030
周立功
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下载文件列表
74hc74/74hc74/designer/impl1/designer.log
74hc74/74hc74/designer/impl1/d_ff.adb
74hc74/74hc74/designer/impl1/d_ff.dtf/verify.log
74hc74/74hc74/designer/impl1/d_ff.ide_des
74hc74/74hc74/designer/impl1/d_ff.pdb
74hc74/74hc74/designer/impl1/d_ff.pdb.depends
74hc74/74hc74/designer/impl1/d_ff.tcl
74hc74/74hc74/designer/impl1/d_ff_fp/$$FlashPro_07294.L$$
74hc74/74hc74/designer/impl1/d_ff_fp/d_ff.log
74hc74/74hc74/designer/impl1/d_ff_fp/d_ff.pro
74hc74/74hc74/designer/impl1/d_ff_fp/projectData/d_ff.pdb
74hc74/74hc74/d_ff.prj
74hc74/74hc74/hdl/d_ff.v
74hc74/74hc74/simulation/modelsim.ini
74hc74/74hc74/simulation/modelsim.ini.sav
74hc74/74hc74/smartgen/smartgen.aws
74hc74/74hc74/synthesis/backup/d_ff.srr
74hc74/74hc74/synthesis/d_ff.areasrr
74hc74/74hc74/synthesis/d_ff.edn
74hc74/74hc74/synthesis/d_ff.htm
74hc74/74hc74/synthesis/d_ff.map
74hc74/74hc74/synthesis/d_ff.pdc
74hc74/74hc74/synthesis/d_ff.sdf
74hc74/74hc74/synthesis/d_ff.so
74hc74/74hc74/synthesis/d_ff.srd
74hc74/74hc74/synthesis/d_ff.srm
74hc74/74hc74/synthesis/d_ff.srr
74hc74/74hc74/synthesis/d_ff.srs
74hc74/74hc74/synthesis/d_ff.szr
74hc74/74hc74/synthesis/d_ff.tlg
74hc74/74hc74/synthesis/d_ff_sdc.sdc
74hc74/74hc74/synthesis/d_ff_syn.prj
74hc74/74hc74/synthesis/run_options.txt
74hc74/74hc74/synthesis/stdout.log
74hc74/74hc74/synthesis/syntmp/d_ff.plg
74hc74/74hc74/synthesis/syntmp/d_ff_flink.htm
74hc74/74hc74/synthesis/syntmp/d_ff_srr.htm
74hc74/74hc74/synthesis/syntmp/d_ff_toc.htm
74hc74/74hc74/viewdraw/vf/project.lst
74hc74/74hc74/viewdraw/viewdraw.ini
74hc74/74hc74.zip
74hc85/74hc85/74hc85.prj
74hc85/74hc85/designer/impl1/compar4.ide_des
74hc85/74hc85/designer/impl1/compare4.adb
74hc85/74hc85/designer/impl1/compare4.dtf/verify.log
74hc85/74hc85/designer/impl1/compare4.ide_des
74hc85/74hc85/designer/impl1/compare4.pdb
74hc85/74hc85/designer/impl1/compare4.pdb.depends
74hc85/74hc85/designer/impl1/compare4.tcl
74hc85/74hc85/designer/impl1/compare4_fp/$$FlashPro_07294.L$$
74hc85/74hc85/designer/impl1/compare4_fp/compare4.log
74hc85/74hc85/designer/impl1/compare4_fp/compare4.pro
74hc85/74hc85/designer/impl1/compare4_fp/projectData/compare4.pdb
74hc85/74hc85/designer/impl1/designer.log
74hc85/74hc85/hdl/74hc85.v
74hc85/74hc85/simulation/modelsim.ini
74hc85/74hc85/simulation/modelsim.ini.sav
74hc85/74hc85/simulation/modelsim.log
74hc85/74hc85/simulation/presynth/compar4/verilog.psm
74hc85/74hc85/simulation/presynth/compar4/_primary.dat
74hc85/74hc85/simulation/presynth/compar4/_primary.dbs
74hc85/74hc85/simulation/presynth/compar4/_primary.vhd
74hc85/74hc85/simulation/presynth/compare4/verilog.psm
74hc85/74hc85/simulation/presynth/compare4/_primary.dat
74hc85/74hc85/simulation/presynth/compare4/_primary.dbs
74hc85/74hc85/simulation/presynth/compare4/_primary.vhd
74hc85/74hc85/simulation/presynth/testbench/verilog.psm
74hc85/74hc85/simulation/presynth/testbench/_primary.dat
74hc85/74hc85/simulation/presynth/testbench/_primary.dbs
74hc85/74hc85/simulation/presynth/testbench/_primary.vhd
74hc85/74hc85/simulation/presynth/_info
74hc85/74hc85/simulation/run.do
74hc85/74hc85/simulation/vsim.wlf
74hc85/74hc85/smartgen/smartgen.aws
74hc85/74hc85/stimulus/testbench.v
74hc85/74hc85/synthesis/.recordref
74hc85/74hc85/synthesis/compare4.areasrr
74hc85/74hc85/synthesis/compare4.edn
74hc85/74hc85/synthesis/compare4.fse
74hc85/74hc85/synthesis/compare4.htm
74hc85/74hc85/synthesis/compare4.map
74hc85/74hc85/synthesis/compare4.pdc
74hc85/74hc85/synthesis/compare4.sap
74hc85/74hc85/synthesis/compare4.sdf
74hc85/74hc85/synthesis/compare4.so
74hc85/74hc85/synthesis/compare4.srd
74hc85/74hc85/synthesis/compare4.srm
74hc85/74hc85/synthesis/compare4.srr
74hc85/74hc85/synthesis/compare4.srs
74hc85/74hc85/synthesis/compare4.szr
74hc85/74hc85/synthesis/compare4.tlg
74hc85/74hc85/synthesis/compare4_sdc.sdc
74hc85/74hc85/synthesis/compare4_syn.prj
74hc85/74hc85/synthesis/run_options.txt
74hc85/74hc85/synthesis/stdout.log
74hc85/74hc85/synthesis/syntmp/compare4.plg
74hc85/74hc85/synthesis/syntmp/compare4_flink.htm
74hc85/74hc85/synthesis/syntmp/compare4_srr.htm
74hc85/74hc85/synthesis/syntmp/compare4_toc.htm
74hc85/74hc85/synthesis/syntmp/sap.log
74hc85/74hc85/synthesis/traplog.tlg
74hc85/74hc85/viewdraw/vf/project.lst
74hc85/74hc85/viewdraw/viewdraw.ini
74hc85/74hc85.pdf
74hc85/74hc85.zip
74hc138/74hc138.pdf
74hc138/74hc138.prj
74hc138/74hc138.prj.convert.8.5.bak
74hc138/designer/impl1/decoder_38.adb
74hc138/designer/impl1/decoder_38.dtf/verify.log
74hc138/designer/impl1/decoder_38.ide_des
74hc138/designer/impl1/decoder_38.pdb
74hc138/designer/impl1/decoder_38.pdb.depends
74hc138/designer/impl1/decoder_38.tcl
74hc138/designer/impl1/decoder_38_1_fp/decoder_38.log
74hc138/designer/impl1/decoder_38_1_fp/decoder_38.pro
74hc138/designer/impl1/decoder_38_ba.sdf
74hc138/designer/impl1/decoder_38_ba.v
74hc138/designer/impl1/decoder_38_fp/decoder_38.pro
74hc138/designer/impl1/designer.log
74hc138/hdl/74hc138.v
74hc138/simulation/modelsim.ini
74hc138/simulation/modelsim.ini.sav
74hc138/simulation/modelsim.log
74hc138/simulation/presynth/decoder_38/verilog.psm
74hc138/simulation/presynth/decoder_38/_primary.dat
7
74hc74/74hc74/designer/impl1/d_ff.adb
74hc74/74hc74/designer/impl1/d_ff.dtf/verify.log
74hc74/74hc74/designer/impl1/d_ff.ide_des
74hc74/74hc74/designer/impl1/d_ff.pdb
74hc74/74hc74/designer/impl1/d_ff.pdb.depends
74hc74/74hc74/designer/impl1/d_ff.tcl
74hc74/74hc74/designer/impl1/d_ff_fp/$$FlashPro_07294.L$$
74hc74/74hc74/designer/impl1/d_ff_fp/d_ff.log
74hc74/74hc74/designer/impl1/d_ff_fp/d_ff.pro
74hc74/74hc74/designer/impl1/d_ff_fp/projectData/d_ff.pdb
74hc74/74hc74/d_ff.prj
74hc74/74hc74/hdl/d_ff.v
74hc74/74hc74/simulation/modelsim.ini
74hc74/74hc74/simulation/modelsim.ini.sav
74hc74/74hc74/smartgen/smartgen.aws
74hc74/74hc74/synthesis/backup/d_ff.srr
74hc74/74hc74/synthesis/d_ff.areasrr
74hc74/74hc74/synthesis/d_ff.edn
74hc74/74hc74/synthesis/d_ff.htm
74hc74/74hc74/synthesis/d_ff.map
74hc74/74hc74/synthesis/d_ff.pdc
74hc74/74hc74/synthesis/d_ff.sdf
74hc74/74hc74/synthesis/d_ff.so
74hc74/74hc74/synthesis/d_ff.srd
74hc74/74hc74/synthesis/d_ff.srm
74hc74/74hc74/synthesis/d_ff.srr
74hc74/74hc74/synthesis/d_ff.srs
74hc74/74hc74/synthesis/d_ff.szr
74hc74/74hc74/synthesis/d_ff.tlg
74hc74/74hc74/synthesis/d_ff_sdc.sdc
74hc74/74hc74/synthesis/d_ff_syn.prj
74hc74/74hc74/synthesis/run_options.txt
74hc74/74hc74/synthesis/stdout.log
74hc74/74hc74/synthesis/syntmp/d_ff.plg
74hc74/74hc74/synthesis/syntmp/d_ff_flink.htm
74hc74/74hc74/synthesis/syntmp/d_ff_srr.htm
74hc74/74hc74/synthesis/syntmp/d_ff_toc.htm
74hc74/74hc74/viewdraw/vf/project.lst
74hc74/74hc74/viewdraw/viewdraw.ini
74hc74/74hc74.zip
74hc85/74hc85/74hc85.prj
74hc85/74hc85/designer/impl1/compar4.ide_des
74hc85/74hc85/designer/impl1/compare4.adb
74hc85/74hc85/designer/impl1/compare4.dtf/verify.log
74hc85/74hc85/designer/impl1/compare4.ide_des
74hc85/74hc85/designer/impl1/compare4.pdb
74hc85/74hc85/designer/impl1/compare4.pdb.depends
74hc85/74hc85/designer/impl1/compare4.tcl
74hc85/74hc85/designer/impl1/compare4_fp/$$FlashPro_07294.L$$
74hc85/74hc85/designer/impl1/compare4_fp/compare4.log
74hc85/74hc85/designer/impl1/compare4_fp/compare4.pro
74hc85/74hc85/designer/impl1/compare4_fp/projectData/compare4.pdb
74hc85/74hc85/designer/impl1/designer.log
74hc85/74hc85/hdl/74hc85.v
74hc85/74hc85/simulation/modelsim.ini
74hc85/74hc85/simulation/modelsim.ini.sav
74hc85/74hc85/simulation/modelsim.log
74hc85/74hc85/simulation/presynth/compar4/verilog.psm
74hc85/74hc85/simulation/presynth/compar4/_primary.dat
74hc85/74hc85/simulation/presynth/compar4/_primary.dbs
74hc85/74hc85/simulation/presynth/compar4/_primary.vhd
74hc85/74hc85/simulation/presynth/compare4/verilog.psm
74hc85/74hc85/simulation/presynth/compare4/_primary.dat
74hc85/74hc85/simulation/presynth/compare4/_primary.dbs
74hc85/74hc85/simulation/presynth/compare4/_primary.vhd
74hc85/74hc85/simulation/presynth/testbench/verilog.psm
74hc85/74hc85/simulation/presynth/testbench/_primary.dat
74hc85/74hc85/simulation/presynth/testbench/_primary.dbs
74hc85/74hc85/simulation/presynth/testbench/_primary.vhd
74hc85/74hc85/simulation/presynth/_info
74hc85/74hc85/simulation/run.do
74hc85/74hc85/simulation/vsim.wlf
74hc85/74hc85/smartgen/smartgen.aws
74hc85/74hc85/stimulus/testbench.v
74hc85/74hc85/synthesis/.recordref
74hc85/74hc85/synthesis/compare4.areasrr
74hc85/74hc85/synthesis/compare4.edn
74hc85/74hc85/synthesis/compare4.fse
74hc85/74hc85/synthesis/compare4.htm
74hc85/74hc85/synthesis/compare4.map
74hc85/74hc85/synthesis/compare4.pdc
74hc85/74hc85/synthesis/compare4.sap
74hc85/74hc85/synthesis/compare4.sdf
74hc85/74hc85/synthesis/compare4.so
74hc85/74hc85/synthesis/compare4.srd
74hc85/74hc85/synthesis/compare4.srm
74hc85/74hc85/synthesis/compare4.srr
74hc85/74hc85/synthesis/compare4.srs
74hc85/74hc85/synthesis/compare4.szr
74hc85/74hc85/synthesis/compare4.tlg
74hc85/74hc85/synthesis/compare4_sdc.sdc
74hc85/74hc85/synthesis/compare4_syn.prj
74hc85/74hc85/synthesis/run_options.txt
74hc85/74hc85/synthesis/stdout.log
74hc85/74hc85/synthesis/syntmp/compare4.plg
74hc85/74hc85/synthesis/syntmp/compare4_flink.htm
74hc85/74hc85/synthesis/syntmp/compare4_srr.htm
74hc85/74hc85/synthesis/syntmp/compare4_toc.htm
74hc85/74hc85/synthesis/syntmp/sap.log
74hc85/74hc85/synthesis/traplog.tlg
74hc85/74hc85/viewdraw/vf/project.lst
74hc85/74hc85/viewdraw/viewdraw.ini
74hc85/74hc85.pdf
74hc85/74hc85.zip
74hc138/74hc138.pdf
74hc138/74hc138.prj
74hc138/74hc138.prj.convert.8.5.bak
74hc138/designer/impl1/decoder_38.adb
74hc138/designer/impl1/decoder_38.dtf/verify.log
74hc138/designer/impl1/decoder_38.ide_des
74hc138/designer/impl1/decoder_38.pdb
74hc138/designer/impl1/decoder_38.pdb.depends
74hc138/designer/impl1/decoder_38.tcl
74hc138/designer/impl1/decoder_38_1_fp/decoder_38.log
74hc138/designer/impl1/decoder_38_1_fp/decoder_38.pro
74hc138/designer/impl1/decoder_38_ba.sdf
74hc138/designer/impl1/decoder_38_ba.v
74hc138/designer/impl1/decoder_38_fp/decoder_38.pro
74hc138/designer/impl1/designer.log
74hc138/hdl/74hc138.v
74hc138/simulation/modelsim.ini
74hc138/simulation/modelsim.ini.sav
74hc138/simulation/modelsim.log
74hc138/simulation/presynth/decoder_38/verilog.psm
74hc138/simulation/presynth/decoder_38/_primary.dat
7
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