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文件名称:flash02

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  • 上传时间:
    2012-09-04
  • 文件大小:
    1.23mb
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一个我自己写的FPGA读写FLASH代码,在QUARTUS 下用verilog编写,falsh的型号是k9f5608u0d,经测试可以用。-I wrote a FLASH FPGA to read and write code, written in QUARTUS next with verilog, falsh model is k9f5608u0d, can be tested.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

flash02/db/flash.(0).cnf.cdb
flash02/db/flash.(0).cnf.hdb
flash02/db/flash.asm.qmsg
flash02/db/flash.asm.rdb
flash02/db/flash.cbx.xml
flash02/db/flash.cmp.bpm
flash02/db/flash.cmp.cdb
flash02/db/flash.cmp.ecobp
flash02/db/flash.cmp.hdb
flash02/db/flash.cmp.kpt
flash02/db/flash.cmp.logdb
flash02/db/flash.cmp.rdb
flash02/db/flash.cmp.tdb
flash02/db/flash.cmp0.ddb
flash02/db/flash.cmp_merge.kpt
flash02/db/flash.db_info
flash02/db/flash.eco.cdb
flash02/db/flash.eda.qmsg
flash02/db/flash.fit.qmsg
flash02/db/flash.hier_info
flash02/db/flash.hif
flash02/db/flash.lpc.html
flash02/db/flash.lpc.rdb
flash02/db/flash.lpc.txt
flash02/db/flash.map.bpm
flash02/db/flash.map.cdb
flash02/db/flash.map.ecobp
flash02/db/flash.map.hdb
flash02/db/flash.map.kpt
flash02/db/flash.map.logdb
flash02/db/flash.map.qmsg
flash02/db/flash.map_bb.cdb
flash02/db/flash.map_bb.hdb
flash02/db/flash.map_bb.logdb
flash02/db/flash.merge.qmsg
flash02/db/flash.pre_map.cdb
flash02/db/flash.pre_map.hdb
flash02/db/flash.rtlv.hdb
flash02/db/flash.rtlv_sg.cdb
flash02/db/flash.rtlv_sg_swap.cdb
flash02/db/flash.sgdiff.cdb
flash02/db/flash.sgdiff.hdb
flash02/db/flash.sld_design_entry.sci
flash02/db/flash.sld_design_entry_dsc.sci
flash02/db/flash.smart_action.txt
flash02/db/flash.smp_dump.txt
flash02/db/flash.syn_hier_info
flash02/db/flash.tan.qmsg
flash02/db/flash.tis_db_list.ddb
flash02/db/logic_util_heursitic.dat
flash02/db/prev_cmp_flash.asm.qmsg
flash02/db/prev_cmp_flash.eda.qmsg
flash02/db/prev_cmp_flash.fit.qmsg
flash02/db/prev_cmp_flash.map.qmsg
flash02/db/prev_cmp_flash.merge.qmsg
flash02/db/prev_cmp_flash.qmsg
flash02/db/prev_cmp_flash.tan.qmsg
flash02/flash.asm.rpt
flash02/flash.done
flash02/flash.dpf
flash02/flash.eda.rpt
flash02/flash.fit.rpt
flash02/flash.fit.smsg
flash02/flash.fit.summary
flash02/flash.flow.rpt
flash02/flash.map.rpt
flash02/flash.map.summary
flash02/flash.merge.rpt
flash02/flash.pin
flash02/flash.pof
flash02/flash.qpf
flash02/flash.qsf
flash02/flash.qws
flash02/flash.sof
flash02/flash.tan.rpt
flash02/flash.tan.summary
flash02/flash.v
flash02/flash.v.bak
flash02/flash_nativelink_simulation.rpt
flash02/incremental_db/compiled_partitions/flash.root_partition.cmp.cdb
flash02/incremental_db/compiled_partitions/flash.root_partition.cmp.dfp
flash02/incremental_db/compiled_partitions/flash.root_partition.cmp.hdb
flash02/incremental_db/compiled_partitions/flash.root_partition.cmp.kpt
flash02/incremental_db/compiled_partitions/flash.root_partition.cmp.logdb
flash02/incremental_db/compiled_partitions/flash.root_partition.cmp.rcfdb
flash02/incremental_db/compiled_partitions/flash.root_partition.cmp.re.rcfdb
flash02/incremental_db/compiled_partitions/flash.root_partition.map.cdb
flash02/incremental_db/compiled_partitions/flash.root_partition.map.dpi
flash02/incremental_db/compiled_partitions/flash.root_partition.map.hdb
flash02/incremental_db/compiled_partitions/flash.root_partition.map.kpt
flash02/incremental_db/README
flash02/simulation/modelsim/flash.sft
flash02/simulation/modelsim/flash.vo
flash02/simulation/modelsim/flash.vt
flash02/simulation/modelsim/flash.vt.bak
flash02/simulation/modelsim/flash_modelsim.xrf
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak1
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak10
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak11
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak2
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak3
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak4
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak5
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak6
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak7
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak8
flash02/simulation/modelsim/flash_run_msim_rtl_verilog.do.bak9
flash02/simulation/modelsim/flash_v.sdo
flash02/simulation/modelsim/modelsim.ini
flash02/simulation/modelsim/msim_transcript
flash02/simulation/modelsim/rtl_work/flash/verilog.prw
flash02/simulation/modelsim/rtl_work/flash/verilog.psm
flash02/simulation/modelsim/rtl_work/flash/_primary.dat
flash02/simulation/modelsim/rtl_work/flash/_primary.dbs
flash02/simulation/modelsim/rtl_work/flash/_primary.vhd
flash02/simulation/modelsim/rtl_work/tst/verilog.prw
flash02/simulation/modelsim/rtl_work/tst/verilog.psm
flash02/simulation/modelsim/rtl_work/tst/_primary.dat
flash02/simulation/modelsim/rtl_work/tst/_primary.dbs
flash02/simulation/modelsim/rtl_work/tst/_primary.vhd
flash02/simulation/modelsim/rtl_work/_info
flash02/simulation/modelsim/rtl_work/_vmake
flash02/simulation/modelsim/vsim.wlf
flash02/simulation/modelsim/rtl_work/flash
flash02/simulation/modelsim/rtl_work/tst
flash02/simulation/modelsim/rtl_work/_temp
flash02/simulation/modelsim/rtl_work
flash02/incremental_db/compiled_partitions
flash02/simulation/modelsim
flash02/db
flash02/incremental_db
flash02/simulation
flash02

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