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文件名称:DupalPortRam.rar

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [WORD]
  • 上传时间：
    2012-09-04
  • 文件大小：
    121.61kb
  • 已下载：
    0次
  • 提 供 者：
    崔****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

基于quartus的双端口RAM的完整设计流程，包括建立的工程仿真实现,Quartus-based dual-port RAM of the integrity of the design process, including the establishment of the Engineering Simulation
相关搜索： 双端口RAM

(系统自动生成,下载前可以参看下载内容)

下载文件列表

DupalPortRam/source/mixed/verilog/mux.vhd
DupalPortRam/source/mixed/verilog/mux21.v
DupalPortRam/source/mixed/verilog/reg8.vhd
DupalPortRam/source/mixed/verilog/rotate.vhd
DupalPortRam/source/mixed/verilog/top.v
DupalPortRam/source/mixed/vhdl/mux.v
DupalPortRam/source/mixed/vhdl/mux21.vhd
DupalPortRam/source/mixed/vhdl/reg8.v
DupalPortRam/source/mixed/vhdl/rotate.v
DupalPortRam/source/mixed/vhdl/top.vhd
DupalPortRam/source/verilog/ALU.V
DupalPortRam/source/verilog/HDL_DEMO.V
DupalPortRam/source/VHDL/ALU.VHD
DupalPortRam/source/VHDL/HDL_DEMO.VHD
DupalPortRam/Synplify_Pro/ALU_Syn_2.prd
DupalPortRam/Synplify_Pro/ALU_Syn_2.prj
DupalPortRam/Synplify_Pro/ALU_Syn_demo.prd
DupalPortRam/Synplify_Pro/ALU_Syn_demo.prj
DupalPortRam/Synplify_Pro/ALU_Syn_demo.sdc
DupalPortRam/Synplify_Pro/Mix_src.prd
DupalPortRam/Synplify_Pro/Mix_src_vhdl.prd
DupalPortRam/Synplify_Pro/Mix_src_vhdl.prj
DupalPortRam/Synplify_Pro/Mix_src_vlog.prd
DupalPortRam/Synplify_Pro/Mix_src_vlog.prj
DupalPortRam/Synplify_Pro/MyWorkspace.prd
DupalPortRam/Synplify_Pro/MyWorkspace.prj
DupalPortRam/Synplify_Pro/rev_1/ALU.fse
DupalPortRam/Synplify_Pro/rev_1/ALU.srd
DupalPortRam/Synplify_Pro/rev_1/ALU.srm
DupalPortRam/Synplify_Pro/rev_1/ALU.srr
DupalPortRam/Synplify_Pro/rev_1/ALU.srs
DupalPortRam/Synplify_Pro/rev_1/ALU.sxr
DupalPortRam/Synplify_Pro/rev_1/ALU.tcl
DupalPortRam/Synplify_Pro/rev_1/ALU.tlg
DupalPortRam/Synplify_Pro/rev_1/ALU.vqm
DupalPortRam/Synplify_Pro/rev_1/ALU.xrf
DupalPortRam/Synplify_Pro/rev_1/ALU_cons.tcl
DupalPortRam/Synplify_Pro/rev_1/ALU_rm.tcl
DupalPortRam/Synplify_Pro/rev_1/AutoConstraint_alu.sdc
DupalPortRam/Synplify_Pro/rev_1/fsmviewer.fsm
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.fse
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.srd
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.srm
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.srr
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.srs
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.sxr
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.ta
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.taq
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.tcl
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.tlg
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.vqm
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO.xrf
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO_cons.tcl
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO_rm.tcl
DupalPortRam/Synplify_Pro/rev_1/HDL_DEMO_ta.srm
DupalPortRam/Synplify_Pro/rev_1/syntmp/ALU.plg
DupalPortRam/Synplify_Pro/rev_1/syntmp/HDL_DEMO.plg
DupalPortRam/Synplify_Pro/rev_2/.recordref
DupalPortRam/Synplify_Pro/rev_2/AutoConstraint_top.sdc
DupalPortRam/Synplify_Pro/rev_2/layer0.tlg
DupalPortRam/Synplify_Pro/rev_2/layer1.tlg
DupalPortRam/Synplify_Pro/rev_2/layer2.tlg
DupalPortRam/Synplify_Pro/rev_2/stderr.log
DupalPortRam/Synplify_Pro/rev_2/stdout.log
DupalPortRam/Synplify_Pro/rev_2/syntmp/top.plg
DupalPortRam/Synplify_Pro/rev_2/top.fse
DupalPortRam/Synplify_Pro/rev_2/top.srd
DupalPortRam/Synplify_Pro/rev_2/top.srm
DupalPortRam/Synplify_Pro/rev_2/top.srr
DupalPortRam/Synplify_Pro/rev_2/top.srs
DupalPortRam/Synplify_Pro/rev_2/top.sxr
DupalPortRam/Synplify_Pro/rev_2/top.tcl
DupalPortRam/Synplify_Pro/rev_2/top.vqm
DupalPortRam/Synplify_Pro/rev_2/top.xrf
DupalPortRam/Synplify_Pro/rev_2/top_cons.tcl
DupalPortRam/Synplify_Pro/rev_2/top_rm.tcl
DupalPortRam/Synplify_Pro/rev_3/.recordref
DupalPortRam/Synplify_Pro/rev_3/layer0.tlg
DupalPortRam/Synplify_Pro/rev_3/layer1.tlg
DupalPortRam/Synplify_Pro/rev_3/layer2.tlg
DupalPortRam/Synplify_Pro/rev_3/stderr.log
DupalPortRam/Synplify_Pro/rev_3/stdout.log
DupalPortRam/Synplify_Pro/rev_3/syntmp/mux.plg
DupalPortRam/Synplify_Pro/rev_3/syntmp/rotate.plg
DupalPortRam/Synplify_Pro/rev_3/syntmp/top.plg
DupalPortRam/Synplify_Pro/rev_3/syntmp/top1.plg
DupalPortRam/Synplify_Pro/rev_3/top1.fse
DupalPortRam/Synplify_Pro/rev_3/top1.srd
DupalPortRam/Synplify_Pro/rev_3/top1.srm
DupalPortRam/Synplify_Pro/rev_3/top1.srr
DupalPortRam/Synplify_Pro/rev_3/top1.srs
DupalPortRam/Synplify_Pro/rev_3/top1.sxr
DupalPortRam/Synplify_Pro/rev_3/top1.tcl
DupalPortRam/Synplify_Pro/rev_3/top1.vqm
DupalPortRam/Synplify_Pro/rev_3/top1.xrf
DupalPortRam/Synplify_Pro/rev_3/top1_cons.tcl
DupalPortRam/Synplify_Pro/rev_3/top1_rm.tcl
DupalPortRam/Synplify_Pro/source/mixed/verilog/mux.vhd
DupalPortRam/Synplify_Pro/source/mixed/verilog/mux21.v
DupalPortRam/Synplify_Pro/source/mixed/verilog/reg8.vhd
DupalPortRam/Synplify_Pro/source/mixed/verilog/rotate.vhd
DupalPortRam/Synplify_Pro/source/mixed/verilog/top.v
DupalPortRam/Synplify_Pro/source/mixed/vhdl/mux.v
DupalPortRam/Synplify_Pro/source/mixed/vhdl/mux21.vhd
DupalPortRam/Synplify_Pro/source/mixed/vhdl/reg8.v
DupalPortRam/Synplify_Pro/source/mixed/vhdl/rotate.v
DupalPortRam/Synplify_Pro/source/mixed/vhdl/top.vhd
DupalPortRam/Synplify_Pro/source/verilog/ALU.V
DupalPortRam/Synplify_Pro/source/verilog/HDL_DEMO.V
DupalPortRam/Synplify_Pro/source/VHDL/ALU.VHD
DupalPortRam/Synplify_Pro/source/VHDL/HDL_DEMO.VHD
DupalPortRam/示例说明.doc
DupalPortRam/Synplify_Pro/source/mixed/verilog
DupalPortRam/Synplify_Pro/source/mixed/vhdl
DupalPortRam/source/mixed/verilog
DupalPortRam/source/mixed/vhdl
DupalPortRam/Synplify_Pro/rev_1/syntmp
DupalPortRam/Synplify_Pro/

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