文件名称:baseband_verilog.rar
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- 上传时间：2012-09-04
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verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter
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下载文件列表
baseband_verilog/accumulator.v
baseband_verilog/carrier_mixer.v
baseband_verilog/carrier_nco.v
baseband_verilog/code_gen2.v
baseband_verilog/code_nco.v
baseband_verilog/epoch_counter.v
baseband_verilog/gps_baseband.v
baseband_verilog/lgpl.txt
baseband_verilog/time_base.v
baseband_verilog/tracking_channel.v
baseband_verilog
baseband_verilog/carrier_mixer.v
baseband_verilog/carrier_nco.v
baseband_verilog/code_gen2.v
baseband_verilog/code_nco.v
baseband_verilog/epoch_counter.v
baseband_verilog/gps_baseband.v
baseband_verilog/lgpl.txt
baseband_verilog/time_base.v
baseband_verilog/tracking_channel.v
baseband_verilog
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