文件名称:FIFO
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- 上传时间:2012-09-04
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文件大小:108.24kb
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基于FPGA的FIFO控制器的设计与实现,ISE,verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
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下载文件列表
FIFO/fifo.cr.mti
FIFO/fifo.mpf
FIFO/generic_fifo_sc.v
FIFO/note.txt
FIFO/test_bench_top.v
FIFO/timescale.v
FIFO/transcript
FIFO/work/_info
FIFO/work/test_bench_top/verilog.asm
FIFO/work/test_bench_top/_primary.dat
FIFO/work/test_bench_top/_primary.vhd
FIFO/work/lfsr/verilog.asm
FIFO/work/lfsr/_primary.dat
FIFO/work/lfsr/_primary.vhd
FIFO/work/generic_fifo_sc_a/verilog.asm
FIFO/work/generic_fifo_sc_a/_primary.dat
FIFO/work/generic_fifo_sc_a/_primary.vhd
FIFO/work/generic_fifo_sc/verilog.asm
FIFO/work/generic_fifo_sc/_primary.dat
FIFO/work/generic_fifo_sc/_primary.vhd
FIFO/work/generic_fifo_lfsr/verilog.asm
FIFO/work/generic_fifo_lfsr/_primary.dat
FIFO/work/generic_fifo_lfsr/_primary.vhd
FIFO/work/generic_fifo_dc_gray/verilog.asm
FIFO/work/generic_fifo_dc_gray/_primary.dat
FIFO/work/generic_fifo_dc_gray/_primary.vhd
FIFO/work/generic_fifo_dc/verilog.asm
FIFO/work/generic_fifo_dc/_primary.dat
FIFO/work/generic_fifo_dc/_primary.vhd
FIFO/work/generic_dpram/verilog.asm
FIFO/work/generic_dpram/_primary.dat
FIFO/work/generic_dpram/_primary.vhd
FIFO/chart/图9-10.bmp
FIFO/chart/图9-4.bmp
FIFO/chart/图9-5.bmp
FIFO/chart/图9-6.bmp
FIFO/chart/图9-9.bmp
FIFO/work/test_bench_top
FIFO/work/lfsr
FIFO/work/generic_fifo_sc_a
FIFO/work/generic_fifo_sc
FIFO/work/generic_fifo_lfsr
FIFO/work/generic_fifo_dc_gray
FIFO/work/generic_fifo_dc
FIFO/work/generic_dpram
FIFO/work
FIFO/chart
FIFO
FIFO/fifo.mpf
FIFO/generic_fifo_sc.v
FIFO/note.txt
FIFO/test_bench_top.v
FIFO/timescale.v
FIFO/transcript
FIFO/work/_info
FIFO/work/test_bench_top/verilog.asm
FIFO/work/test_bench_top/_primary.dat
FIFO/work/test_bench_top/_primary.vhd
FIFO/work/lfsr/verilog.asm
FIFO/work/lfsr/_primary.dat
FIFO/work/lfsr/_primary.vhd
FIFO/work/generic_fifo_sc_a/verilog.asm
FIFO/work/generic_fifo_sc_a/_primary.dat
FIFO/work/generic_fifo_sc_a/_primary.vhd
FIFO/work/generic_fifo_sc/verilog.asm
FIFO/work/generic_fifo_sc/_primary.dat
FIFO/work/generic_fifo_sc/_primary.vhd
FIFO/work/generic_fifo_lfsr/verilog.asm
FIFO/work/generic_fifo_lfsr/_primary.dat
FIFO/work/generic_fifo_lfsr/_primary.vhd
FIFO/work/generic_fifo_dc_gray/verilog.asm
FIFO/work/generic_fifo_dc_gray/_primary.dat
FIFO/work/generic_fifo_dc_gray/_primary.vhd
FIFO/work/generic_fifo_dc/verilog.asm
FIFO/work/generic_fifo_dc/_primary.dat
FIFO/work/generic_fifo_dc/_primary.vhd
FIFO/work/generic_dpram/verilog.asm
FIFO/work/generic_dpram/_primary.dat
FIFO/work/generic_dpram/_primary.vhd
FIFO/chart/图9-10.bmp
FIFO/chart/图9-4.bmp
FIFO/chart/图9-5.bmp
FIFO/chart/图9-6.bmp
FIFO/chart/图9-9.bmp
FIFO/work/test_bench_top
FIFO/work/lfsr
FIFO/work/generic_fifo_sc_a
FIFO/work/generic_fifo_sc
FIFO/work/generic_fifo_lfsr
FIFO/work/generic_fifo_dc_gray
FIFO/work/generic_fifo_dc
FIFO/work/generic_dpram
FIFO/work
FIFO/chart
FIFO
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