文件名称:This VHDL code pertains to the DCO model
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C.1 DCO LEVEL 2
This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between lines 19 and 30. The port declaration of the block’s I/O signals is between lines 31 and 39. The behavioral architecture describing the block starts at line 42. Lines 43 through 49 declare internal signals. Lines 56 through 61 describe the DCO varactor merging operation on the left of Fig. 6.10. The period is calculated and checked for upper and lower bounds between lines 67 and 81. Finally, the period-controlled oscillator
(PCO) engine is instantiated between lines 87 and 98.
C.1 DCO LEVEL 2
This VHDL code pertains to the DCO model descr iption in Section 6.5.5. The entity declaration of the level 2 DCO is between lines 18 and 39. The VHDL generics or elaboration-phase parameter constants are declared between lines 19 and 30. The port declaration of the block’s I/O signals is between lines 31 and 39. The behavioral architecture describing the block starts at line 42. Lines 43 through 49 declare internal signals. Lines 56 through 61 describe the DCO varactor merging operation on the left of Fig. 6.10. The period is calculated and checked for upper and lower bounds between lines 67 and 81. Finally, the period-controlled oscillator
(PCO) engine is instantiated between lines 87 and 98.
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