文件名称:RiscCpu
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- 上传时间:2012-09-29
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文件大小:9.62kb
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Verilog-RISC CPU 代码
实现了简单的RISC cpu,可供初学者参考,学习硬件描述语言,及设计方法。该程序通过了modelsim仿真验证。
北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted ModelSim simulation. BUAA
实现了简单的RISC cpu,可供初学者参考,学习硬件描述语言,及设计方法。该程序通过了modelsim仿真验证。
北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted ModelSim simulation. BUAA
相关搜索: cpu verilog
verilog cpu
RISC CPU
risc
risc verilog
vhdl risc
verilog
risccpu
RISC VHDL
cpu design
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下载文件列表
RiscCpu
RiscCpu/accum.v
RiscCpu/addr_decode.v
RiscCpu/adr.v
RiscCpu/alu.v
RiscCpu/clk_gen.v
RiscCpu/counter.v
RiscCpu/cpu.v
RiscCpu/cputop.v
RiscCpu/datactl.v
RiscCpu/machine.v
RiscCpu/machinectl.v
RiscCpu/ram.v
RiscCpu/register.v
RiscCpu/rom.v
RiscCpu/test1.dat
RiscCpu/test1.pro
RiscCpu/test2.dat
RiscCpu/test2.pro
RiscCpu/test3.dat
RiscCpu/test3.pro
RiscCpu/transcript
RiscCpu/accum.v
RiscCpu/addr_decode.v
RiscCpu/adr.v
RiscCpu/alu.v
RiscCpu/clk_gen.v
RiscCpu/counter.v
RiscCpu/cpu.v
RiscCpu/cputop.v
RiscCpu/datactl.v
RiscCpu/machine.v
RiscCpu/machinectl.v
RiscCpu/ram.v
RiscCpu/register.v
RiscCpu/rom.v
RiscCpu/test1.dat
RiscCpu/test1.pro
RiscCpu/test2.dat
RiscCpu/test2.pro
RiscCpu/test3.dat
RiscCpu/test3.pro
RiscCpu/transcript
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