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文件名称:CORE8051_ADC_OK_328

  • 所属分类：
    Other systems
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-10-07
  • 文件大小：
    14.57mb
  • 已下载：
    1次
  • 提 供 者：
    冰***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

这是一个在Fusion系列的AFS600的FPGA，在里面嵌入51核和12位adc模块，可以在lcd12864上显示，能正常转换电压。做adc使用。-This is a AFS600 at the Fusion series FPGA, embedded in which 51 nuclear and 12-bit adc module, you can show up at lcd12864 to the normal voltage conversion. Does the use of adc.
相关搜索： AFS600 adc conversion vhdl

(系统自动生成,下载前可以参看下载内容)

下载文件列表

CORE8051_ADC_OK_328/3.28.txt
CORE8051_ADC_OK_328/cnt.v
CORE8051_ADC_OK_328/constraint/TOP_CORE8051_sdc.sdc
CORE8051_ADC_OK_328/core8051.hex
CORE8051_ADC_OK_328/CORE8051_ROM_OK.prj
CORE8051_ADC_OK_328/designer/impl1/ada00224-1.tmp
CORE8051_ADC_OK_328/designer/impl1/designer.log
CORE8051_ADC_OK_328/designer/impl1/designer_genhdl.log
CORE8051_ADC_OK_328/designer/impl1/sdcrd.log
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/@t@o@p_@f@p@g@a/verilog.psm
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/@t@o@p_@f@p@g@a/_primary.dat
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/@t@o@p_@f@p@g@a/_primary.dbs
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/@t@o@p_@f@p@g@a/_primary.vhd
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/stimulus/verilog.psm
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/stimulus/_primary.dat
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/stimulus/_primary.dbs
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/stimulus/_primary.vhd
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/tb_clock_minmax/verilog.psm
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dat
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.dbs
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/tb_clock_minmax/_primary.vhd
CORE8051_ADC_OK_328/designer/impl1/simulation/postlayout/_info
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051.adb
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051.dtf/verify.log
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051.ide_des
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051.pdb
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051.pdb.depends
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051.tcl
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_1.adb
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_1.dtf/verify.log
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_1.ide_des
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_1.pdb
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_1.pdb.depends
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_1_ba.sdf
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_1_ba.v
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_ba.sdf
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_ba.v
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_fp/$$FlashPro_FPBBALTLPT1.L$$
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_fp/projectData/TOP_CORE8051.pdb
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_fp/TOP_CORE8051.log
CORE8051_ADC_OK_328/designer/impl1/TOP_CORE8051_fp/TOP_CORE8051.pro
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA.adb
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA.dtf/verify.log
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA.ide_des
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA.pdb
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA.pdb.depends
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA.plk
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA.tcl
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA_ba.sdf
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA_ba.v
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA_fp/$$FlashPro_FPBBALTLPT1.L$$
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA_fp/projectData/TOP_FPGA.pdb
CORE8051_ADC_OK_328/designer/impl1/TOP_FPGA_fp/TOP_FPGA.pro
CORE8051_ADC_OK_328/designer/impl1/unsav.lok
CORE8051_ADC_OK_328/filter_20ms.v
CORE8051_ADC_OK_328/hdl/core8051_oci0_withoutio_pa3.v
CORE8051_ADC_OK_328/hdl/Core8051_ROM_Ctr.v
CORE8051_ADC_OK_328/hdl/TOP_ADC.v
CORE8051_ADC_OK_328/hdl/TOP_CORE8051.v
CORE8051_ADC_OK_328/hdl/TOP_FPGA.v
CORE8051_ADC_OK_328/simulation/modelsim.ini
CORE8051_ADC_OK_328/simulation/modelsim.ini.sav
CORE8051_ADC_OK_328/simulation/modelsim.log
CORE8051_ADC_OK_328/simulation/MY_ADC_acm_ram_R0C0.mem
CORE8051_ADC_OK_328/simulation/MY_ADC_calibip_wrapper_R0C0.mem
CORE8051_ADC_OK_328/simulation/RAM256X8_R0C0.mem
CORE8051_ADC_OK_328/simulation/ROM64K.mem
CORE8051_ADC_OK_328/simulation/Rom_Data_bus.hex
CORE8051_ADC_OK_328/simulation/run.do
CORE8051_ADC_OK_328/simulation/vsim.wlf
CORE8051_ADC_OK_328/smartgen/common/commonFileInventory.xml
CORE8051_ADC_OK_328/smartgen/common/verilog/calibip.v
CORE8051_ADC_OK_328/smartgen/common/verilog/calibip_brentkung_24.v
CORE8051_ADC_OK_328/smartgen/common/verilog/calibip_CLRAM.v
CORE8051_ADC_OK_328/smartgen/common/verilog/calibip_compute_block.v
CORE8051_ADC_OK_328/smartgen/common/verilog/calibip_ram512x9_afs.v
CORE8051_ADC_OK_328/smartgen/common/verilog/calibip_ripple_24.v
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC.cfg
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC.cxf
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC.gen
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC.log
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC.ncf
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC.v
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC_acm.mem
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC_acm_ram.hex
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC_acm_ram_R0C0.mem
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC_calibcoefficient.mem
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC_calibip_wrapper.hex
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC_calibip_wrapper.v
CORE8051_ADC_OK_328/smartgen/MY_ADC/MY_ADC

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