文件名称:c8051
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- 上传时间:2012-10-09
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文件大小:1.02mb
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下载文件列表
doc/c8051_a.pdf
doc/c8051_spec_ok.pdf
doc/c8051.pdf
doc/c8051_spec.pdf
doc/c8051_dsn.pdf
doc/c8051_b.pdf
src_verilog/core/.xhdl3.comp.xref
src_verilog/core/CLOCK_CONTROL_R.v
src_verilog/core/SERIAL_R.v
src_verilog/core/C8051_S.v
src_verilog/core/.xhdl3_data/control_unit.symb
src_verilog/core/.xhdl3_data/ram_sfr_control.code
src_verilog/core/.xhdl3_data/isr.code
src_verilog/core/.xhdl3_data/serial.symb
src_verilog/core/.xhdl3_data/utility.code
src_verilog/core/.xhdl3_data/clock_control.code
src_verilog/core/.xhdl3_data/oci.code
src_verilog/core/.xhdl3_data/ports.symb
src_verilog/core/.xhdl3_data/alu.code
src_verilog/core/.xhdl3_data/timer_0_1.symb
src_verilog/core/.xhdl3_data/oci.symb
src_verilog/core/.xhdl3_data/timer_0_1.code
src_verilog/core/.xhdl3_data/alu.symb
src_verilog/core/.xhdl3_data/control_unit.code
src_verilog/core/.xhdl3_data/memory_control.symb
src_verilog/core/.xhdl3_data/clock_control.symb
src_verilog/core/.xhdl3_data/memory_control.code
src_verilog/core/.xhdl3_data/ports.code
src_verilog/core/.xhdl3_data/serial.code
src_verilog/core/.xhdl3_data/utility.symb
src_verilog/core/.xhdl3_data/c8051.symb
src_verilog/core/.xhdl3_data/c8051.code
src_verilog/core/.xhdl3_data/isr.symb
src_verilog/core/.xhdl3_data/ram_sfr_control.symb
src_verilog/core/TIMER_0_1_R.v
src_verilog/core/ALU_R.v
src_verilog/core/OCI_R.v
src_verilog/core/UTILITY.v
src_verilog/core/PORTS_R.v
src_verilog/core/ISR_R.v
src_verilog/core/RAM_SFR_CONTROL_R.v
src_verilog/core/CONTROL_UNIT_R.v
src_verilog/core/MEMORY_CONTROL_R.v
src_verilog/tb/.xhdl3.comp.xref
src_verilog/tb/tb.v
src_verilog/tb/.xhdl3_data/tb_c8051.code
src_verilog/tb/.xhdl3_data/tb_c8051.symb
src_verilog/tb/chip/.xhdl3.comp.xref
src_verilog/tb/chip/utility.v
src_verilog/tb/chip/chippad.v
src_verilog/tb/chip/chipsfr.v
src_verilog/tb/chip/chiprom.v
src_verilog/tb/chip/chip8051.v
src_verilog/tb/chip/chipram.v
src_verilog/tb/chip/.xhdl3_data/internal_open_drain.symb
src_verilog/tb/chip/.xhdl3_data/chip_oci.symb
src_verilog/tb/chip/.xhdl3_data/utility.code
src_verilog/tb/chip/.xhdl3_data/special_function_register.code
src_verilog/tb/chip/.xhdl3_data/special_function_register.symb
src_verilog/tb/chip/.xhdl3_data/internal_open_drain.code
src_verilog/tb/chip/.xhdl3_data/internal_data_memory.code
src_verilog/tb/chip/.xhdl3_data/internal_data_memory.symb
src_verilog/tb/chip/.xhdl3_data/internal_program_memory.symb
src_verilog/tb/chip/.xhdl3_data/chip_oci.code
src_verilog/tb/chip/.xhdl3_data/chip_c8051.code
src_verilog/tb/chip/.xhdl3_data/internal_program_memory.code
src_verilog/tb/chip/.xhdl3_data/chip_c8051.symb
src_verilog/tb/chip/.xhdl3_data/utility.symb
src_verilog/tb/chip/chipoci.v
tests/default/acscomp.txt
tests/default/test.asm
tests/default/time.txt
tests/default/simdiff.txt
tests/default/stim.txt
tests/default/introm.hex
tests/default/extrom.hex
tests/default/simcomp.txt
tests/default/acsdiff.txt
src_verilog/tb/chip/.xhdl3_data
src_verilog/core/.xhdl3_data
src_verilog/tb/.xhdl3_data
src_verilog/tb/chip
src_verilog/core
src_verilog/tb
tests/default
doc
src_verilog
tests
doc/c8051_spec_ok.pdf
doc/c8051.pdf
doc/c8051_spec.pdf
doc/c8051_dsn.pdf
doc/c8051_b.pdf
src_verilog/core/.xhdl3.comp.xref
src_verilog/core/CLOCK_CONTROL_R.v
src_verilog/core/SERIAL_R.v
src_verilog/core/C8051_S.v
src_verilog/core/.xhdl3_data/control_unit.symb
src_verilog/core/.xhdl3_data/ram_sfr_control.code
src_verilog/core/.xhdl3_data/isr.code
src_verilog/core/.xhdl3_data/serial.symb
src_verilog/core/.xhdl3_data/utility.code
src_verilog/core/.xhdl3_data/clock_control.code
src_verilog/core/.xhdl3_data/oci.code
src_verilog/core/.xhdl3_data/ports.symb
src_verilog/core/.xhdl3_data/alu.code
src_verilog/core/.xhdl3_data/timer_0_1.symb
src_verilog/core/.xhdl3_data/oci.symb
src_verilog/core/.xhdl3_data/timer_0_1.code
src_verilog/core/.xhdl3_data/alu.symb
src_verilog/core/.xhdl3_data/control_unit.code
src_verilog/core/.xhdl3_data/memory_control.symb
src_verilog/core/.xhdl3_data/clock_control.symb
src_verilog/core/.xhdl3_data/memory_control.code
src_verilog/core/.xhdl3_data/ports.code
src_verilog/core/.xhdl3_data/serial.code
src_verilog/core/.xhdl3_data/utility.symb
src_verilog/core/.xhdl3_data/c8051.symb
src_verilog/core/.xhdl3_data/c8051.code
src_verilog/core/.xhdl3_data/isr.symb
src_verilog/core/.xhdl3_data/ram_sfr_control.symb
src_verilog/core/TIMER_0_1_R.v
src_verilog/core/ALU_R.v
src_verilog/core/OCI_R.v
src_verilog/core/UTILITY.v
src_verilog/core/PORTS_R.v
src_verilog/core/ISR_R.v
src_verilog/core/RAM_SFR_CONTROL_R.v
src_verilog/core/CONTROL_UNIT_R.v
src_verilog/core/MEMORY_CONTROL_R.v
src_verilog/tb/.xhdl3.comp.xref
src_verilog/tb/tb.v
src_verilog/tb/.xhdl3_data/tb_c8051.code
src_verilog/tb/.xhdl3_data/tb_c8051.symb
src_verilog/tb/chip/.xhdl3.comp.xref
src_verilog/tb/chip/utility.v
src_verilog/tb/chip/chippad.v
src_verilog/tb/chip/chipsfr.v
src_verilog/tb/chip/chiprom.v
src_verilog/tb/chip/chip8051.v
src_verilog/tb/chip/chipram.v
src_verilog/tb/chip/.xhdl3_data/internal_open_drain.symb
src_verilog/tb/chip/.xhdl3_data/chip_oci.symb
src_verilog/tb/chip/.xhdl3_data/utility.code
src_verilog/tb/chip/.xhdl3_data/special_function_register.code
src_verilog/tb/chip/.xhdl3_data/special_function_register.symb
src_verilog/tb/chip/.xhdl3_data/internal_open_drain.code
src_verilog/tb/chip/.xhdl3_data/internal_data_memory.code
src_verilog/tb/chip/.xhdl3_data/internal_data_memory.symb
src_verilog/tb/chip/.xhdl3_data/internal_program_memory.symb
src_verilog/tb/chip/.xhdl3_data/chip_oci.code
src_verilog/tb/chip/.xhdl3_data/chip_c8051.code
src_verilog/tb/chip/.xhdl3_data/internal_program_memory.code
src_verilog/tb/chip/.xhdl3_data/chip_c8051.symb
src_verilog/tb/chip/.xhdl3_data/utility.symb
src_verilog/tb/chip/chipoci.v
tests/default/acscomp.txt
tests/default/test.asm
tests/default/time.txt
tests/default/simdiff.txt
tests/default/stim.txt
tests/default/introm.hex
tests/default/extrom.hex
tests/default/simcomp.txt
tests/default/acsdiff.txt
src_verilog/tb/chip/.xhdl3_data
src_verilog/core/.xhdl3_data
src_verilog/tb/.xhdl3_data
src_verilog/tb/chip
src_verilog/core
src_verilog/tb
tests/default
doc
src_verilog
tests
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