利用QuartusII的"MegaWizard Plug-In Manager",

设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE

把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行

时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。



2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER，

设计一个20bit的up_only COUNTER,

要求该COUNTER在FE0FA和FFFFF之间自动循环计数；

分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、

EPF10K70RC240-4几种芯片中的最大工作频率；

请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来

（仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the　MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the　MegaWizard Plug-In Manager　in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF　analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency　I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency).