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文件名称:uart

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  • 上传时间:
    2012-10-16
  • 文件大小:
    548.13kb
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    0次
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介绍说明--下载内容来自于网络,使用问题请自行百度

Verilog实现串口收发数据,包括整个quartus工程-Verilog serial port to send and receive data, including the whole quartus project
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart/clk_com.v
uart/clk_com.v.bak
uart/com_con.v
uart/com_con.v.bak
uart/com_rx.v
uart/com_rx.v.bak
uart/com_top.v
uart/com_tx.v
uart/com_tx.v.bak
uart/db/prev_cmp_uart.asm.qmsg
uart/db/prev_cmp_uart.eda.qmsg
uart/db/prev_cmp_uart.fit.qmsg
uart/db/prev_cmp_uart.map.qmsg
uart/db/prev_cmp_uart.qmsg
uart/db/prev_cmp_uart.tan.qmsg
uart/db/uart.(0).cnf.cdb
uart/db/uart.(0).cnf.hdb
uart/db/uart.(1).cnf.cdb
uart/db/uart.(1).cnf.hdb
uart/db/uart.(2).cnf.cdb
uart/db/uart.(2).cnf.hdb
uart/db/uart.(3).cnf.cdb
uart/db/uart.(3).cnf.hdb
uart/db/uart.(4).cnf.cdb
uart/db/uart.(4).cnf.hdb
uart/db/uart.ace_cmp.bpm
uart/db/uart.ace_cmp.cdb
uart/db/uart.ace_cmp.ecobp
uart/db/uart.ace_cmp.hdb
uart/db/uart.asm.qmsg
uart/db/uart.cbx.xml
uart/db/uart.cmp.bpm
uart/db/uart.cmp.cdb
uart/db/uart.cmp.ecobp
uart/db/uart.cmp.hdb
uart/db/uart.cmp.kpt
uart/db/uart.cmp.logdb
uart/db/uart.cmp.rdb
uart/db/uart.cmp_merge.kpt
uart/db/uart.db_info
uart/db/uart.eco.cdb
uart/db/uart.eda.qmsg
uart/db/uart.fit.qmsg
uart/db/uart.fnsim.hdb
uart/db/uart.fnsim.qmsg
uart/db/uart.hier_info
uart/db/uart.hif
uart/db/uart.map.bpm
uart/db/uart.map.cdb
uart/db/uart.map.ecobp
uart/db/uart.map.hdb
uart/db/uart.map.kpt
uart/db/uart.map.logdb
uart/db/uart.map.qmsg
uart/db/uart.map_bb.cdb
uart/db/uart.map_bb.hdb
uart/db/uart.map_bb.hdbx
uart/db/uart.map_bb.logdb
uart/db/uart.pre_map.cdb
uart/db/uart.pre_map.hdb
uart/db/uart.psp
uart/db/uart.rpp.qmsg
uart/db/uart.rtlv.hdb
uart/db/uart.rtlv_sg.cdb
uart/db/uart.rtlv_sg_swap.cdb
uart/db/uart.sgate.rvd
uart/db/uart.sgate_sm.rvd
uart/db/uart.sgdiff.cdb
uart/db/uart.sgdiff.hdb
uart/db/uart.sld_design_entry.sci
uart/db/uart.sld_design_entry_dsc.sci
uart/db/uart.syn_hier_info
uart/db/uart.tan.qmsg
uart/db/uart.tis_db_list.ddb
uart/db/uart.tmw_info
uart/incremental_db/compiled_partitions/uart.root_partition.cmp.atm
uart/incremental_db/compiled_partitions/uart.root_partition.cmp.dfp
uart/incremental_db/compiled_partitions/uart.root_partition.cmp.hdbx
uart/incremental_db/compiled_partitions/uart.root_partition.cmp.kpt
uart/incremental_db/compiled_partitions/uart.root_partition.cmp.logdb
uart/incremental_db/compiled_partitions/uart.root_partition.cmp.rcf
uart/incremental_db/compiled_partitions/uart.root_partition.map.atm
uart/incremental_db/compiled_partitions/uart.root_partition.map.dpi
uart/incremental_db/compiled_partitions/uart.root_partition.map.hdbx
uart/incremental_db/compiled_partitions/uart.root_partition.map.kpt
uart/incremental_db/README
uart/simulation/modelsim/cycloneii_atoms.v
uart/simulation/modelsim/testbench.v
uart/simulation/modelsim/uart.sft
uart/simulation/modelsim/uart.vo
uart/simulation/modelsim/uart_modelsim.xrf
uart/simulation/modelsim/uart_v.sdo
uart/testbench.v
uart/testbench.v.bak
uart/timing/custom/uart.vo
uart/timing/custom/uart_v.sdo
uart/uart.asm.rpt
uart/uart.cdf
uart/uart.done
uart/uart.dpf
uart/uart.eda.rpt
uart/uart.fit.rpt
uart/uart.fit.smsg
uart/uart.fit.summary
uart/uart.flow.rpt
uart/uart.map.rpt
uart/uart.map.summary
uart/uart.pin
uart/uart.pof
uart/uart.qpf
uart/uart.qsf
uart/uart.qws
uart/uart.sof
uart/uart.tan.rpt
uart/uart.tan.summary
uart/vish_stacktrace.vstf
uart/vsim.wlf
uart/work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.dat
uart/work/@c@y@c@l@o@n@e@i@i_@p@r@i@m_@d@f@f@e/_primary.vhd
uart/work/clk_com/verilog.asm
uart/work/clk_com/_primary.dat
uart/work/clk_com/_primary.vhd
uart/work/com_con/verilog.asm
uart/work/com_con/_primary.dat
uart/work/com_con/_primary.vhd
uart/work/com_rx/verilog.asm
uart/work/com_rx/_primary.dat
uart/work/com_rx/_primary.vhd
uart/work/com_tx/verilog.asm
uart/work/com_tx/_primary.dat
uart/work/com_tx/_primary.vhd
uart/work/cycloneii_and1/_primary.dat
uart/work/cycloneii_and1/_primary.vhd
uart/work/cycloneii_and16/_primary.dat
uart/work/cycloneii_and16/_primary.vhd
uart/work/cycloneii_asmiblock/_primary.dat
uart/work/cycloneii_asmiblock/_primary.vhd
uart/work/cycloneii_asynch_io/_primary.dat
uart/work/cycloneii_asynch_io/_primary.vhd
uart/work/cycloneii_b17mux21/_primary.dat
uart/work/cycloneii_b17mux21/_primary.vhd
uart/work/cycloneii_b5mux21/_primary.dat
uart/work/cycloneii_b5mux21/_primary.vhd
uart/work/cycloneii_bmux21/_primary.dat
uart/work/cycloneii_bmux21/_primary.vhd
uart/work/cycloneii_clkctrl/_primary.dat
uart/work/cycloneii_clkctrl/_primary.vhd
uart/work/cycloneii_clk_delay_cal_ctrl/_primary.dat
uart/work/cycloneii_clk_delay_cal_ctrl/_primary.vhd
uart/work/cycloneii_clk_delay_ctrl/_primary.dat
uart/work/cycloneii_clk_delay_ctrl/_primary.vhd
uart/work/cycloneii_crcblock/_primary.dat
uart/work/cycloneii_crcblock/_primary.vhd
uart/work/cycloneii_dffe/_primary.dat
uart/work/cycloneii_dffe/_primary.vhd
uart/work/cycloneii_ena_reg/_primary.dat
uart/work/cycloneii_ena_reg/_primary.vhd
uart/work/cycloneii_io/_primary.dat
uart/work/cycloneii_io/_primary.vhd
uart/work/cycloneii_jtag/_primary.dat
uart/work/cycloneii_jtag/_primary.vhd
uart/work/cycloneii_latch/_primary.dat
uart/work/cycloneii_latch/_primary.vhd
uart/work/cycloneii_lcell_comb/_primary.dat
uart/work/cycloneii_lcell_comb/_primary.vhd
uart/work/cycloneii_lcell_ff/_primary.dat
uart/work/cycloneii_lcell_ff/_pr

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