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文件名称:Verilog-pci

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  • 上传时间:
    2012-10-17
  • 文件大小:
    5.26mb
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    3次
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介绍说明--下载内容来自于网络,使用问题请自行百度

PCI的FPGA实现,使用verilog硬件描述语言模拟pci数据接口的数据传输过程。-PCI simulation with FPGA, using the verilog hardware describing language to simulate data transfer processes on pci data interface.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

pci/bus_commands.v
pci/i2c_slave_model.v
pci/pci_async_reset_flop.v
pci/pci_behavioral_pci2pci_bridge.v
pci/pci_behaviorial_device.v
pci/pci_behaviorial_master.v
pci/pci_behaviorial_target.v
pci/pci_bench_common_tasks.v
pci/pci_blue_arbiter.v
pci/pci_blue_constants.sv
pci/pci_blue_options.sv
pci/pci_bridge32.v
pci/pci_bus_monitor.v
pci/pci_cbe_en_crit.v
pci/pci_conf_cyc_addr_dec.v
pci/pci_conf_space.v
pci/pci_constants.v
pci/pci_cur_out_reg.v
pci/pci_delayed_sync.v
pci/pci_delayed_write_reg.v
pci/pci_frame_crit.v
pci/pci_frame_en_crit.v
pci/pci_frame_load_crit.v
pci/pci_in_reg.v
pci/pci_io_mux.v
pci/pci_io_mux_ad_en_crit.v
pci/pci_io_mux_ad_load_crit.v
pci/pci_irdy_out_crit.v
pci/pci_master32_sm.v
pci/pci_master32_sm_if.v
pci/pci_mas_ad_en_crit.v
pci/pci_mas_ad_load_crit.v
pci/pci_mas_ch_state_crit.v
pci/pci_out_reg.v
pci/pci_parity_check.v
pci/pci_par_crit.v
pci/pci_pcir_fifo_control.v
pci/pci_pciw_fifo_control.v
pci/pci_pciw_pcir_fifos.v
pci/pci_pci_decoder.v
pci/pci_pci_tpram.v
pci/pci_perr_crit.v
pci/pci_perr_en_crit.v
pci/pci_ram_16x40d.v
pci/pci_regression_constants.v
pci/pci_rst_int.v
pci/pci_serr_crit.v
pci/pci_serr_en_crit.v
pci/pci_spoci_ctrl.v
pci/pci_synchronizer_flop.v
pci/pci_sync_module.v
pci/pci_target32_clk_en.v
pci/pci_target32_devs_crit.v
pci/pci_target32_interface.v
pci/pci_target32_sm.v
pci/pci_target32_stop_crit.v
pci/pci_target32_trdy_crit.v
pci/pci_target_unit.v
pci/pci_testbench_defines.v
pci/pci_top.cr.mti
pci/pci_top.mpf
pci/pci_unsupported_commands_master.v
pci/pci_user_constants.v
pci/pci_user_constants.v.bak
pci/pci_wbr_fifo_control.v
pci/pci_wbs_wbb3_2_wbb2.v
pci/pci_wbw_fifo_control.v
pci/pci_wbw_wbr_fifos.v
pci/pci_wb_addr_mux.v
pci/pci_wb_decoder.v
pci/pci_wb_master.v
pci/pci_wb_slave.v
pci/pci_wb_slave_unit.v
pci/pci_wb_tpram.v
pci/system.v
pci/timescale.v
pci/top.v
pci/transcript
pci/vsim.dbg
pci/vsim.wlf
pci/wave.do
pci/wb_bus_mon.v
pci/wb_master32.v
pci/wb_master_behavioral.v
pci/wb_slave_behavioral.v
pci/work/_info
pci/work/system/verilog.asm
pci/work/system/_primary.dat
pci/work/system/_primary.vhd
pci/work/pci_wb_tpram/verilog.asm
pci/work/pci_wb_tpram/_primary.dat
pci/work/pci_wb_tpram/_primary.vhd
pci/work/pci_wb_slave_unit/verilog.asm
pci/work/pci_wb_slave_unit/_primary.dat
pci/work/pci_wb_slave_unit/_primary.vhd
pci/work/pci_wb_slave/verilog.asm
pci/work/pci_wb_slave/_primary.dat
pci/work/pci_wb_slave/_primary.vhd
pci/work/pci_wb_master/verilog.asm
pci/work/pci_wb_master/_primary.dat
pci/work/pci_wb_master/_primary.vhd
pci/work/pci_wb_decoder/verilog.asm
pci/work/pci_wb_decoder/_primary.dat
pci/work/pci_wb_decoder/_primary.vhd
pci/work/pci_wb_addr_mux/verilog.asm
pci/work/pci_wb_addr_mux/_primary.dat
pci/work/pci_wb_addr_mux/_primary.vhd
pci/work/pci_wbw_wbr_fifos/verilog.asm
pci/work/pci_wbw_wbr_fifos/_primary.dat
pci/work/pci_wbw_wbr_fifos/_primary.vhd
pci/work/pci_wbw_fifo_control/verilog.asm
pci/work/pci_wbw_fifo_control/_primary.dat
pci/work/pci_wbw_fifo_control/_primary.vhd
pci/work/pci_wbs_wbb3_2_wbb2/verilog.asm
pci/work/pci_wbs_wbb3_2_wbb2/_primary.dat
pci/work/pci_wbs_wbb3_2_wbb2/_primary.vhd
pci/work/pci_wbr_fifo_control/verilog.asm
pci/work/pci_wbr_fifo_control/_primary.dat
pci/work/pci_wbr_fifo_control/_primary.vhd
pci/work/pci_unsupported_commands_master/verilog.asm
pci/work/pci_unsupported_commands_master/_primary.dat
pci/work/pci_unsupported_commands_master/_primary.vhd
pci/work/pci_target_unit/verilog.asm
pci/work/pci_target_unit/_primary.dat
pci/work/pci_target_unit/_primary.vhd
pci/work/pci_target32_trdy_crit/verilog.asm
pci/work/pci_target32_trdy_crit/_primary.dat
pci/work/pci_target32_trdy_crit/_primary.vhd
pci/work/pci_target32_stop_crit/verilog.asm
pci/work/pci_target32_stop_crit/_primary.dat
pci/work/pci_target32_stop_crit/_primary.vhd
pci/work/pci_target32_sm/verilog.asm
pci/work/pci_target32_sm/_primary.dat
pci/work/pci_target32_sm/_primary.vhd
pci/work/pci_target32_interface/verilog.asm
pci/work/pci_target32_interface/_primary.dat
pci/work/pci_target32_interface/_primary.vhd
pci/work/pci_target32_devs_crit/verilog.asm
pci/work/pci_target32_devs_crit/_primary.dat
pci/work/pci_target32_devs_crit/_primary.vhd
pci/work/pci_target32_clk_en/verilog.asm
pci/work/pci_target32_clk_en/_primary.dat
pci/work/pci_target32_clk_en/_primary.vhd
pci/work/pci_sync_module/verilog.asm
pci/work/pci_sync_module/_primary.dat
pci/work/pci_sync_module/_primary.vhd
pci/work/pci_synchronizer_flop/verilog.asm
pci/work/pci_synchronizer_flop/_primary.dat
pci/work/pci_synchronizer_flop/_primary.vhd
pci/work/pci_spoci_ctrl/_primary.dat
pci/work/pci_spoci_ctrl/_primary.vhd
pci/work/pci_serr_en_crit/verilog.asm
pci/work/pci_serr_en_crit/_primary.dat
pci/work/pci_serr_en_crit/_primary.vhd
pci/work/pci_serr_crit/verilog.asm
pci/work/pci_serr_crit/_primary.dat
pci/work/pci_serr_crit/_primary.vhd
pci/work/pci_rst_int/verilog.asm
pci/work/pci_rst_int/_primary.dat
pci/work/pci_rst_int/_primary.vhd
pci/work/pci_ram_16x40d/_primary.dat
pci/work/pci_ram_16x40d/_primary.vhd
pci/work/pci_perr_en_crit/verilog.asm
pci/work/pci_perr_en_crit/_primary.dat
pci/work/pci_perr_en_crit/_primary.vhd
pci/work/

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