文件名称:FPGA_UART
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- 上传时间:2012-10-19
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文件大小:5.75mb
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已下载:0次
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相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
其中讲到的是经典的VHDL的UART设计实例,而且有很详细的解释和分析,适合针对FPGA串口的开发。-Which is referred to the UART VHDL design of the classic examples, and there are detailed explanation and analysis for the serial port for FPGA development.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FPGA_UART/SAVE2006-5-27_22-35-17.TXT
FPGA_UART/SAVE2006-5-29_23-28-32.TXT
FPGA_UART/sscom.ini
FPGA_UART/SSCOM32.EXE
FPGA_UART/基于VerilogHDL的UARTIP的设计.pdf
FPGA_UART/基于Verilog_HDL的UART串行通讯模块设计及仿真.pdf
FPGA_UART/CODE/PCM编解码器的软件实现.pdf
FPGA_UART/CODE/基于FPGA的PCM帧同步检测及告警电路的设计.pdf
FPGA_UART/CODE/基于FPGA的PCM编码器与解码器的设计与实现.pdf
FPGA_UART/CODE/基于FPGA的可编程PCM采编器的实现.pdf
FPGA_UART/CODE/基于FPGA的小数分频器的实现.pdf
FPGA_UART/CODE/基于FPGA的数字通信系统帧同步电路设计.pdf
FPGA_UART/CODE/基于VerilogHDL的PCM采编器设计与实现.pdf
FPGA_UART/CODE/基于帧同步问题的一堂精品课设计.pdf
FPGA_UART/CODE/uart/具有中断管理功能的多UART控制器设计.pdf
FPGA_UART/CODE/uart/基于ASIC_SoC的UART核的设计.kdh
FPGA_UART/CODE/uart/基于FPGA的UARTIP核设计与实现.pdf
FPGA_UART/CODE/uart/基于FPGA的简化UART电路设计.pdf
FPGA_UART/CODE/uart/基于VerilogHDL的UARTIP的设计.pdf
FPGA_UART/CODE/uart/基于Verilog_HDL的UART串行通讯模块设计及仿真.pdf
FPGA_UART/CODE/uart/基于有限状态机实现全双工可编程UART.pdf
FPGA_UART/FPGA_UART_DRIVER/asm.h
FPGA_UART/FPGA_UART_DRIVER/config.h
FPGA_UART/FPGA_UART_DRIVER/garfield.h
FPGA_UART/FPGA_UART_DRIVER/gpio.h
FPGA_UART/FPGA_UART_DRIVER/HA_print.c
FPGA_UART/FPGA_UART_DRIVER/head_gfd.s
FPGA_UART/FPGA_UART_DRIVER/heap.s
FPGA_UART/FPGA_UART_DRIVER/intc.H
FPGA_UART/FPGA_UART_DRIVER/int_gfd.s
FPGA_UART/FPGA_UART_DRIVER/int_vec_handler.c
FPGA_UART/FPGA_UART_DRIVER/retarget.c
FPGA_UART/FPGA_UART_DRIVER/scat_crremap.scf
FPGA_UART/FPGA_UART_DRIVER/stack.s
FPGA_UART/FPGA_UART_DRIVER/system.c
FPGA_UART/FPGA_UART_DRIVER/system.h
FPGA_UART/FPGA_UART_DRIVER/typedef.h
FPGA_UART/FPGA_UART_DRIVER/uart.c
FPGA_UART/FPGA_UART_DRIVER/uart.h
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart.mcp
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/CWSettingsWindows.stg
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/Debug/TargetDataWindows.tdt
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/fpga_uart.axf
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/TargetDataWindows.tdt
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/head_gfd.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/int_gfd.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/int_vec_handler.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/retarget.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/system.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/uart.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/Release/TargetDataWindows.tdt
FPGA_UART/VERILOG_CODE/fpga_top.qsf
FPGA_UART/VERILOG_CODE/代码说明.txt
FPGA_UART/VERILOG_CODE/proj/cmp_state.ini
FPGA_UART/VERILOG_CODE/proj/fpga_top.asm.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.cdf
FPGA_UART/VERILOG_CODE/proj/fpga_top.done
FPGA_UART/VERILOG_CODE/proj/fpga_top.fit.eqn
FPGA_UART/VERILOG_CODE/proj/fpga_top.fit.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.flow.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.hexout
FPGA_UART/VERILOG_CODE/proj/fpga_top.map.eqn
FPGA_UART/VERILOG_CODE/proj/fpga_top.map.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.pin
FPGA_UART/VERILOG_CODE/proj/fpga_top.pof
FPGA_UART/VERILOG_CODE/proj/fpga_top.prd
FPGA_UART/VERILOG_CODE/proj/fpga_top.prj
FPGA_UART/VERILOG_CODE/proj/fpga_top.qpf
FPGA_UART/VERILOG_CODE/proj/fpga_top.qsf
FPGA_UART/VERILOG_CODE/proj/fpga_top.qws
FPGA_UART/VERILOG_CODE/proj/fpga_top.sim.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.sof
FPGA_UART/VERILOG_CODE/proj/fpga_top.tan.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.tan.summary
FPGA_UART/VERILOG_CODE/proj/fpga_top_assignment_defaults.qdf
FPGA_UART/VERILOG_CODE/proj/output.pof
FPGA_UART/VERILOG_CODE/proj/output_file.pof
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(0).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(0).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(1).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(1).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(10).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(10).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(11).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(11).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(12).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(12).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(13).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(13).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(14).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(14).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(15).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(15).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(16).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(16).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(17).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(17).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(18).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(18).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(19).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(19).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(2).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(2).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(20).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(20).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(21).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(21).cnf.hdb
FPGA_UART/VERILO
FPGA_UART/SAVE2006-5-29_23-28-32.TXT
FPGA_UART/sscom.ini
FPGA_UART/SSCOM32.EXE
FPGA_UART/基于VerilogHDL的UARTIP的设计.pdf
FPGA_UART/基于Verilog_HDL的UART串行通讯模块设计及仿真.pdf
FPGA_UART/CODE/PCM编解码器的软件实现.pdf
FPGA_UART/CODE/基于FPGA的PCM帧同步检测及告警电路的设计.pdf
FPGA_UART/CODE/基于FPGA的PCM编码器与解码器的设计与实现.pdf
FPGA_UART/CODE/基于FPGA的可编程PCM采编器的实现.pdf
FPGA_UART/CODE/基于FPGA的小数分频器的实现.pdf
FPGA_UART/CODE/基于FPGA的数字通信系统帧同步电路设计.pdf
FPGA_UART/CODE/基于VerilogHDL的PCM采编器设计与实现.pdf
FPGA_UART/CODE/基于帧同步问题的一堂精品课设计.pdf
FPGA_UART/CODE/uart/具有中断管理功能的多UART控制器设计.pdf
FPGA_UART/CODE/uart/基于ASIC_SoC的UART核的设计.kdh
FPGA_UART/CODE/uart/基于FPGA的UARTIP核设计与实现.pdf
FPGA_UART/CODE/uart/基于FPGA的简化UART电路设计.pdf
FPGA_UART/CODE/uart/基于VerilogHDL的UARTIP的设计.pdf
FPGA_UART/CODE/uart/基于Verilog_HDL的UART串行通讯模块设计及仿真.pdf
FPGA_UART/CODE/uart/基于有限状态机实现全双工可编程UART.pdf
FPGA_UART/FPGA_UART_DRIVER/asm.h
FPGA_UART/FPGA_UART_DRIVER/config.h
FPGA_UART/FPGA_UART_DRIVER/garfield.h
FPGA_UART/FPGA_UART_DRIVER/gpio.h
FPGA_UART/FPGA_UART_DRIVER/HA_print.c
FPGA_UART/FPGA_UART_DRIVER/head_gfd.s
FPGA_UART/FPGA_UART_DRIVER/heap.s
FPGA_UART/FPGA_UART_DRIVER/intc.H
FPGA_UART/FPGA_UART_DRIVER/int_gfd.s
FPGA_UART/FPGA_UART_DRIVER/int_vec_handler.c
FPGA_UART/FPGA_UART_DRIVER/retarget.c
FPGA_UART/FPGA_UART_DRIVER/scat_crremap.scf
FPGA_UART/FPGA_UART_DRIVER/stack.s
FPGA_UART/FPGA_UART_DRIVER/system.c
FPGA_UART/FPGA_UART_DRIVER/system.h
FPGA_UART/FPGA_UART_DRIVER/typedef.h
FPGA_UART/FPGA_UART_DRIVER/uart.c
FPGA_UART/FPGA_UART_DRIVER/uart.h
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart.mcp
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/CWSettingsWindows.stg
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/Debug/TargetDataWindows.tdt
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/fpga_uart.axf
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/TargetDataWindows.tdt
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/head_gfd.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/int_gfd.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/int_vec_handler.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/retarget.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/system.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/DebugRel/ObjectCode/uart.o
FPGA_UART/FPGA_UART_DRIVER/fpga_uart/fpga_uart_Data/Release/TargetDataWindows.tdt
FPGA_UART/VERILOG_CODE/fpga_top.qsf
FPGA_UART/VERILOG_CODE/代码说明.txt
FPGA_UART/VERILOG_CODE/proj/cmp_state.ini
FPGA_UART/VERILOG_CODE/proj/fpga_top.asm.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.cdf
FPGA_UART/VERILOG_CODE/proj/fpga_top.done
FPGA_UART/VERILOG_CODE/proj/fpga_top.fit.eqn
FPGA_UART/VERILOG_CODE/proj/fpga_top.fit.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.flow.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.hexout
FPGA_UART/VERILOG_CODE/proj/fpga_top.map.eqn
FPGA_UART/VERILOG_CODE/proj/fpga_top.map.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.pin
FPGA_UART/VERILOG_CODE/proj/fpga_top.pof
FPGA_UART/VERILOG_CODE/proj/fpga_top.prd
FPGA_UART/VERILOG_CODE/proj/fpga_top.prj
FPGA_UART/VERILOG_CODE/proj/fpga_top.qpf
FPGA_UART/VERILOG_CODE/proj/fpga_top.qsf
FPGA_UART/VERILOG_CODE/proj/fpga_top.qws
FPGA_UART/VERILOG_CODE/proj/fpga_top.sim.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.sof
FPGA_UART/VERILOG_CODE/proj/fpga_top.tan.rpt
FPGA_UART/VERILOG_CODE/proj/fpga_top.tan.summary
FPGA_UART/VERILOG_CODE/proj/fpga_top_assignment_defaults.qdf
FPGA_UART/VERILOG_CODE/proj/output.pof
FPGA_UART/VERILOG_CODE/proj/output_file.pof
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(0).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(0).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(1).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(1).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(10).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(10).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(11).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(11).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(12).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(12).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(13).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(13).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(14).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(14).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(15).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(15).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(16).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(16).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(17).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(17).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(18).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(18).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(19).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(19).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(2).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(2).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(20).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(20).cnf.hdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(21).cnf.cdb
FPGA_UART/VERILOG_CODE/proj/db/fpga_top(21).cnf.hdb
FPGA_UART/VERILO
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