文件名称:VHDL
-
所属分类:
- 标签属性:
- 上传时间:2012-10-20
-
文件大小:1.02mb
-
已下载:0次
-
提 供 者:
-
相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
支持十条指令的微处理器 包括add sub mov mvi jmp jz in out sti lda微指令 支持8个寄存器 16位数据总线 地址总线 -Supports 10 microprocessor instructions, including add sub mov mvi jmp jz in out sti lda microinstruction registers support 8 data bus 16-bit address bus
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VHDL/
VHDL/alu.cmd_log
VHDL/alu.lso
VHDL/alu.ngc
VHDL/alu.ngr
VHDL/alu.prj
VHDL/alu.stx
VHDL/alu.syr
VHDL/alu.vhdl
VHDL/automake.log
VHDL/bitgen.ut
VHDL/clock.cmd_log
VHDL/clock.dhp
VHDL/clock.lso
VHDL/clock.ngc
VHDL/clock.ngr
VHDL/clock.npl
VHDL/clock.prj
VHDL/clock.stx
VHDL/clock.syr
VHDL/clock.vhdl
VHDL/control.cmd_log
VHDL/control.lso
VHDL/control.ngc
VHDL/control.ngr
VHDL/control.prj
VHDL/control.stx
VHDL/control.syr
VHDL/control.vhdl
VHDL/coregen.log
VHDL/coregen.prj
VHDL/cpu.bgn
VHDL/cpu.bit
VHDL/cpu.bld
VHDL/cpu.cmd_log
VHDL/cpu.drc
VHDL/cpu.lso
VHDL/cpu.mrp
VHDL/cpu.nc1
VHDL/cpu.ncd
VHDL/cpu.ngc
VHDL/cpu.ngd
VHDL/cpu.ngm
VHDL/cpu.ngr
VHDL/cpu.pad
VHDL/cpu.pad_txt
VHDL/cpu.par
VHDL/cpu.pcf
VHDL/cpu.placed_ncd_tracker
VHDL/cpu.prj
VHDL/cpu.routed_ncd_tracker
VHDL/cpu.stx
VHDL/cpu.syr
VHDL/cpu.twr
VHDL/cpu.twx
VHDL/cpu.ucf
VHDL/cpu.ucf.untf
VHDL/cpu.ut
VHDL/cpu.vhdl
VHDL/cpu.xpi
VHDL/cpu_last_par.ncd
VHDL/cpu_map.ncd
VHDL/cpu_map.ngm
VHDL/cpu_pad.csv
VHDL/cpu_pad.txt
VHDL/getir.cmd_log
VHDL/getir.lso
VHDL/getir.ngc
VHDL/getir.ngr
VHDL/getir.prj
VHDL/getir.stx
VHDL/getir.syr
VHDL/getir.vhdl
VHDL/pepExtractor.prj
VHDL/results.txt
VHDL/rwrite.cmd_log
VHDL/rwrite.lso
VHDL/rwrite.ngc
VHDL/rwrite.ngr
VHDL/rwrite.prj
VHDL/rwrite.stx
VHDL/rwrite.syr
VHDL/rwrite.vhdl
VHDL/store.cmd_log
VHDL/store.lso
VHDL/store.ngc
VHDL/store.ngr
VHDL/store.prj
VHDL/store.stx
VHDL/store.syr
VHDL/store.vhdl
VHDL/Symth.vhdl
VHDL/talu.ANT
VHDL/talu.fdo
VHDL/talu.tbw
VHDL/talu.udo
VHDL/talu.vhw
VHDL/talu1.ANT
VHDL/talu1.fdo
VHDL/talu1.tbw
VHDL/talu1.udo
VHDL/talu1.vhw
VHDL/tclock.ANT
VHDL/tclock.fdo
VHDL/tclock.tbw
VHDL/tclock.udo
VHDL/tclock.vhw
VHDL/tcontrol.ANT
VHDL/tcontrol.fdo
VHDL/tcontrol.tbw
VHDL/tcontrol.udo
VHDL/tcontrol.vhw
VHDL/tcpu.ANT
VHDL/tcpu.fdo
VHDL/tcpu.tbw
VHDL/tcpu.udo
VHDL/tcpu.vhw
VHDL/tgetir.ANT
VHDL/tgetir.fdo
VHDL/tgetir.tbw
VHDL/tgetir.udo
VHDL/tgetir.vhw
VHDL/tgetir2.ANT
VHDL/tgetir2.fdo
VHDL/tgetir2.tbw
VHDL/tgetir2.udo
VHDL/tgetir2.vhw
VHDL/transcript
VHDL/trwrite.ANT
VHDL/trwrite.fdo
VHDL/trwrite.tbw
VHDL/trwrite.udo
VHDL/trwrite.vhw
VHDL/tstore.ANT
VHDL/tstore.fdo
VHDL/tstore.tbw
VHDL/tstore.udo
VHDL/tstore.vhw
VHDL/vsim.wlf
VHDL/work/
VHDL/work/alu/
VHDL/work/alu/behavioral.dat
VHDL/work/alu/behavioral.psm
VHDL/work/alu/_primary.dat
VHDL/work/alu_cfg/
VHDL/work/alu_cfg/_primary.dat
VHDL/work/alu_cfg/_vhdl.psm
VHDL/work/clock/
VHDL/work/clock/behavioral.dat
VHDL/work/clock/behavioral.psm
VHDL/work/clock/_primary.dat
VHDL/work/clock_cfg/
VHDL/work/clock_cfg/_primary.dat
VHDL/work/clock_cfg/_vhdl.psm
VHDL/work/control/
VHDL/work/control/behavioral.dat
VHDL/work/control/behavioral.psm
VHDL/work/control/_primary.dat
VHDL/work/control_cfg/
VHDL/work/control_cfg/_primary.dat
VHDL/work/control_cfg/_vhdl.psm
VHDL/work/cpu/
VHDL/work/cpu/behavioral.dat
VHDL/work/cpu/behavioral.psm
VHDL/work/cpu/_primary.dat
VHDL/work/cpu_cfg/
VHDL/work/cpu_cfg/_primary.dat
VHDL/work/cpu_cfg/_vhdl.psm
VHDL/work/getir/
VHDL/work/getir/behavioral.dat
VHDL/work/getir/behavioral.psm
VHDL/work/getir/_primary.dat
VHDL/work/getir_cfg/
VHDL/work/getir_cfg/_primary.dat
VHDL/work/getir_cfg/_vhdl.psm
VHDL/work/rwrite/
VHDL/work/rwrite/behavioral.dat
VHDL/work/rwrite/behavioral.psm
VHDL/work/rwrite/_primary.dat
VHDL/work/rwrite_cfg/
VHDL/work/rwrite_cfg/_primary.dat
VHDL/work/rwrite_cfg/_vhdl.psm
VHDL/work/store/
VHDL/work/store/behavioral.dat
VHDL/work/store/behavioral.psm
VHDL/work/store/_primary.dat
VHDL/work/store_cfg/
VHDL/work/store_cfg/_primary.dat
VHDL/work/store_cfg/_vhdl.psm
VHDL/work/talu/
VHDL/work/talu1/
VHDL/work/talu1/testbench_arch.dat
VHDL/work/talu1/testbench_arch.psm
VHDL/work/talu1/_primary.dat
VHDL/work/talu/testbench_arch.dat
VHDL/work/talu/testbench_arch.psm
VHDL/work/talu/_primary.dat
VHDL/work/tclock/
VHDL/work/tclock/testbench_arch.dat
VHDL/work/tclock/testbench_arch.psm
VHDL/work/tclock/_primary.dat
VHDL/work/tcontrol/
VHDL/work/tcontrol/testbench_arch.dat
VHDL/work/tcontrol/testbench_arch.psm
VHDL/work/tcontrol/_primary.dat
VHDL/work/tcpu/
VHDL/work/tcpu/testbench_arch.dat
VHDL/work/tcpu/testbench_arch.psm
VHDL/work/tcpu/_primary.dat
VHDL/work/tgetir/
VHDL/work/tgetir2/
VHDL/work/tgetir2/testbench_arch.dat
VHDL/work/tgetir2/testbench_arch.psm
VHDL/work/tgetir2/_primary.dat
VHDL/work/tgetir/testbench_arch.dat
VHDL/work/tgetir/testbench_arch.psm
VHDL/work/tgetir/_primary.dat
VHDL/work/trwrite/
VHDL/work/trwrite/testbench_arch.dat
VHDL/work/trwrite/testbench_arch.psm
VHDL/work/trwrite/_primary.dat
VHDL/work/tstore/
VHDL/work/tstore/testbench_arch.dat
VHDL/work/tstore/testbench_arch.psm
VHDL/work/tstore/_primary.dat
VHDL/work/_info
VHDL/xst/
VHDL/xst/work/
VHDL/xst/work/hdllib.ref
VHDL/xst/work/hdpdeps.ref
VHDL/xst/work/sub00/
VHDL/xst/work/sub00/vhpl00.vho
VHDL/xst/work/sub00/vhpl01.vho
VHDL/xst/work/sub00/vhpl02.vho
VHDL/xst/work/sub00/vhpl03.vho
VHDL/xst/work/sub00/vhpl04.vho
VHDL/xst/work/sub00/vhpl05.vho
VHDL/xst/work/sub00/vhpl06.vho
VHDL/xst/work/sub00/vhpl07.vho
VHDL/xst/work/sub00/vhpl08.vho
VHDL/xst/work/sub00/vhpl09.vho
VHDL/xst/work/sub00/vhpl10.vho
VHDL/xst/work/sub00/vhpl11.vho
VHDL/xst/work/sub00/vhpl12.vho
VHDL/xst/
VHDL/alu.cmd_log
VHDL/alu.lso
VHDL/alu.ngc
VHDL/alu.ngr
VHDL/alu.prj
VHDL/alu.stx
VHDL/alu.syr
VHDL/alu.vhdl
VHDL/automake.log
VHDL/bitgen.ut
VHDL/clock.cmd_log
VHDL/clock.dhp
VHDL/clock.lso
VHDL/clock.ngc
VHDL/clock.ngr
VHDL/clock.npl
VHDL/clock.prj
VHDL/clock.stx
VHDL/clock.syr
VHDL/clock.vhdl
VHDL/control.cmd_log
VHDL/control.lso
VHDL/control.ngc
VHDL/control.ngr
VHDL/control.prj
VHDL/control.stx
VHDL/control.syr
VHDL/control.vhdl
VHDL/coregen.log
VHDL/coregen.prj
VHDL/cpu.bgn
VHDL/cpu.bit
VHDL/cpu.bld
VHDL/cpu.cmd_log
VHDL/cpu.drc
VHDL/cpu.lso
VHDL/cpu.mrp
VHDL/cpu.nc1
VHDL/cpu.ncd
VHDL/cpu.ngc
VHDL/cpu.ngd
VHDL/cpu.ngm
VHDL/cpu.ngr
VHDL/cpu.pad
VHDL/cpu.pad_txt
VHDL/cpu.par
VHDL/cpu.pcf
VHDL/cpu.placed_ncd_tracker
VHDL/cpu.prj
VHDL/cpu.routed_ncd_tracker
VHDL/cpu.stx
VHDL/cpu.syr
VHDL/cpu.twr
VHDL/cpu.twx
VHDL/cpu.ucf
VHDL/cpu.ucf.untf
VHDL/cpu.ut
VHDL/cpu.vhdl
VHDL/cpu.xpi
VHDL/cpu_last_par.ncd
VHDL/cpu_map.ncd
VHDL/cpu_map.ngm
VHDL/cpu_pad.csv
VHDL/cpu_pad.txt
VHDL/getir.cmd_log
VHDL/getir.lso
VHDL/getir.ngc
VHDL/getir.ngr
VHDL/getir.prj
VHDL/getir.stx
VHDL/getir.syr
VHDL/getir.vhdl
VHDL/pepExtractor.prj
VHDL/results.txt
VHDL/rwrite.cmd_log
VHDL/rwrite.lso
VHDL/rwrite.ngc
VHDL/rwrite.ngr
VHDL/rwrite.prj
VHDL/rwrite.stx
VHDL/rwrite.syr
VHDL/rwrite.vhdl
VHDL/store.cmd_log
VHDL/store.lso
VHDL/store.ngc
VHDL/store.ngr
VHDL/store.prj
VHDL/store.stx
VHDL/store.syr
VHDL/store.vhdl
VHDL/Symth.vhdl
VHDL/talu.ANT
VHDL/talu.fdo
VHDL/talu.tbw
VHDL/talu.udo
VHDL/talu.vhw
VHDL/talu1.ANT
VHDL/talu1.fdo
VHDL/talu1.tbw
VHDL/talu1.udo
VHDL/talu1.vhw
VHDL/tclock.ANT
VHDL/tclock.fdo
VHDL/tclock.tbw
VHDL/tclock.udo
VHDL/tclock.vhw
VHDL/tcontrol.ANT
VHDL/tcontrol.fdo
VHDL/tcontrol.tbw
VHDL/tcontrol.udo
VHDL/tcontrol.vhw
VHDL/tcpu.ANT
VHDL/tcpu.fdo
VHDL/tcpu.tbw
VHDL/tcpu.udo
VHDL/tcpu.vhw
VHDL/tgetir.ANT
VHDL/tgetir.fdo
VHDL/tgetir.tbw
VHDL/tgetir.udo
VHDL/tgetir.vhw
VHDL/tgetir2.ANT
VHDL/tgetir2.fdo
VHDL/tgetir2.tbw
VHDL/tgetir2.udo
VHDL/tgetir2.vhw
VHDL/transcript
VHDL/trwrite.ANT
VHDL/trwrite.fdo
VHDL/trwrite.tbw
VHDL/trwrite.udo
VHDL/trwrite.vhw
VHDL/tstore.ANT
VHDL/tstore.fdo
VHDL/tstore.tbw
VHDL/tstore.udo
VHDL/tstore.vhw
VHDL/vsim.wlf
VHDL/work/
VHDL/work/alu/
VHDL/work/alu/behavioral.dat
VHDL/work/alu/behavioral.psm
VHDL/work/alu/_primary.dat
VHDL/work/alu_cfg/
VHDL/work/alu_cfg/_primary.dat
VHDL/work/alu_cfg/_vhdl.psm
VHDL/work/clock/
VHDL/work/clock/behavioral.dat
VHDL/work/clock/behavioral.psm
VHDL/work/clock/_primary.dat
VHDL/work/clock_cfg/
VHDL/work/clock_cfg/_primary.dat
VHDL/work/clock_cfg/_vhdl.psm
VHDL/work/control/
VHDL/work/control/behavioral.dat
VHDL/work/control/behavioral.psm
VHDL/work/control/_primary.dat
VHDL/work/control_cfg/
VHDL/work/control_cfg/_primary.dat
VHDL/work/control_cfg/_vhdl.psm
VHDL/work/cpu/
VHDL/work/cpu/behavioral.dat
VHDL/work/cpu/behavioral.psm
VHDL/work/cpu/_primary.dat
VHDL/work/cpu_cfg/
VHDL/work/cpu_cfg/_primary.dat
VHDL/work/cpu_cfg/_vhdl.psm
VHDL/work/getir/
VHDL/work/getir/behavioral.dat
VHDL/work/getir/behavioral.psm
VHDL/work/getir/_primary.dat
VHDL/work/getir_cfg/
VHDL/work/getir_cfg/_primary.dat
VHDL/work/getir_cfg/_vhdl.psm
VHDL/work/rwrite/
VHDL/work/rwrite/behavioral.dat
VHDL/work/rwrite/behavioral.psm
VHDL/work/rwrite/_primary.dat
VHDL/work/rwrite_cfg/
VHDL/work/rwrite_cfg/_primary.dat
VHDL/work/rwrite_cfg/_vhdl.psm
VHDL/work/store/
VHDL/work/store/behavioral.dat
VHDL/work/store/behavioral.psm
VHDL/work/store/_primary.dat
VHDL/work/store_cfg/
VHDL/work/store_cfg/_primary.dat
VHDL/work/store_cfg/_vhdl.psm
VHDL/work/talu/
VHDL/work/talu1/
VHDL/work/talu1/testbench_arch.dat
VHDL/work/talu1/testbench_arch.psm
VHDL/work/talu1/_primary.dat
VHDL/work/talu/testbench_arch.dat
VHDL/work/talu/testbench_arch.psm
VHDL/work/talu/_primary.dat
VHDL/work/tclock/
VHDL/work/tclock/testbench_arch.dat
VHDL/work/tclock/testbench_arch.psm
VHDL/work/tclock/_primary.dat
VHDL/work/tcontrol/
VHDL/work/tcontrol/testbench_arch.dat
VHDL/work/tcontrol/testbench_arch.psm
VHDL/work/tcontrol/_primary.dat
VHDL/work/tcpu/
VHDL/work/tcpu/testbench_arch.dat
VHDL/work/tcpu/testbench_arch.psm
VHDL/work/tcpu/_primary.dat
VHDL/work/tgetir/
VHDL/work/tgetir2/
VHDL/work/tgetir2/testbench_arch.dat
VHDL/work/tgetir2/testbench_arch.psm
VHDL/work/tgetir2/_primary.dat
VHDL/work/tgetir/testbench_arch.dat
VHDL/work/tgetir/testbench_arch.psm
VHDL/work/tgetir/_primary.dat
VHDL/work/trwrite/
VHDL/work/trwrite/testbench_arch.dat
VHDL/work/trwrite/testbench_arch.psm
VHDL/work/trwrite/_primary.dat
VHDL/work/tstore/
VHDL/work/tstore/testbench_arch.dat
VHDL/work/tstore/testbench_arch.psm
VHDL/work/tstore/_primary.dat
VHDL/work/_info
VHDL/xst/
VHDL/xst/work/
VHDL/xst/work/hdllib.ref
VHDL/xst/work/hdpdeps.ref
VHDL/xst/work/sub00/
VHDL/xst/work/sub00/vhpl00.vho
VHDL/xst/work/sub00/vhpl01.vho
VHDL/xst/work/sub00/vhpl02.vho
VHDL/xst/work/sub00/vhpl03.vho
VHDL/xst/work/sub00/vhpl04.vho
VHDL/xst/work/sub00/vhpl05.vho
VHDL/xst/work/sub00/vhpl06.vho
VHDL/xst/work/sub00/vhpl07.vho
VHDL/xst/work/sub00/vhpl08.vho
VHDL/xst/work/sub00/vhpl09.vho
VHDL/xst/work/sub00/vhpl10.vho
VHDL/xst/work/sub00/vhpl11.vho
VHDL/xst/work/sub00/vhpl12.vho
VHDL/xst/
本网站为编程资源及源代码搜集、介绍的搜索网站,版权归原作者所有! 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.