文件名称:decoder
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- 上传时间:2012-10-26
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文件大小:349.65kb
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已下载:1次
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介绍说明--下载内容来自于网络,使用问题请自行百度
用verilog编写的bch译码器,包括测试文件,随机加载了比特流,进行了测试。-Prepared using Verilog BCH decoder, including test papers, random load the bit stream to carry out the test.
相关搜索: bch verilog
decoder
BCH
bch veril
decoder verilog
verilog bch decoder
Verilog DECODER
bch verilog csdn
(系统自动生成,下载前可以参看下载内容)
下载文件列表
decoder15_summary.html
decoder15_test.v
decoder15_test_v.fdo
decoder15_test_v.udo
oytt.ise
oytt.ise_ISE_Backup
oytt.restore
transcript
vsim.wlf
_xmsgs
work
work/decoder15
work/decoder15/_primary.dat
work/decoder15/_primary.vhd
work/decoder15_test_v
work/decoder15_test_v/_primary.dat
work/decoder15_test_v/_primary.vhd
work/glbl
work/glbl/_primary.dat
work/glbl/_primary.vhd
work/_info
work/_opt
work/_opt/D__Xilinx92i_verilog_mti_se_unisims_ver__info
work/_opt/D__Xilinx92i_verilog_mti_se_XilinxCoreLib_ver__info
work/_opt/work_decoder15_fast.asm
work/_opt/work_decoder15_fast.dt2
work/_opt/work_decoder15_test_v_fast.asm
work/_opt/work_decoder15_test_v_fast.dt2
work/_opt/work_glbl_fast.asm
work/_opt/work_glbl_fast.dt2
work/_opt/work__info
work/_opt/_deps
work/_opt1
work/_opt1/D__Xilinx92i_verilog_mti_se_unisims_ver__info
work/_opt1/D__Xilinx92i_verilog_mti_se_XilinxCoreLib_ver__info
work/_opt1/work_decoder15_fast.asm
work/_opt1/work_decoder15_fast.dt2
work/_opt1/work_decoder15_test_v_fast.asm
work/_opt1/work_decoder15_test_v_fast.dt2
work/_opt1/work__info
work/_opt1/_deps
work/_opt2
work/_opt2/work_decoder15_fast.asm
work/_opt2/work_decoder15_fast.dt2
work/_opt2/work_glbl_fast.asm
work/_opt2/work_glbl_fast.dt2
work/_opt2/work__info
work/_opt2/_deps
work/_temp
decoder15.v
decoder15.udo
decoder15_test.v
decoder15_test_v.fdo
decoder15_test_v.udo
oytt.ise
oytt.ise_ISE_Backup
oytt.restore
transcript
vsim.wlf
_xmsgs
work
work/decoder15
work/decoder15/_primary.dat
work/decoder15/_primary.vhd
work/decoder15_test_v
work/decoder15_test_v/_primary.dat
work/decoder15_test_v/_primary.vhd
work/glbl
work/glbl/_primary.dat
work/glbl/_primary.vhd
work/_info
work/_opt
work/_opt/D__Xilinx92i_verilog_mti_se_unisims_ver__info
work/_opt/D__Xilinx92i_verilog_mti_se_XilinxCoreLib_ver__info
work/_opt/work_decoder15_fast.asm
work/_opt/work_decoder15_fast.dt2
work/_opt/work_decoder15_test_v_fast.asm
work/_opt/work_decoder15_test_v_fast.dt2
work/_opt/work_glbl_fast.asm
work/_opt/work_glbl_fast.dt2
work/_opt/work__info
work/_opt/_deps
work/_opt1
work/_opt1/D__Xilinx92i_verilog_mti_se_unisims_ver__info
work/_opt1/D__Xilinx92i_verilog_mti_se_XilinxCoreLib_ver__info
work/_opt1/work_decoder15_fast.asm
work/_opt1/work_decoder15_fast.dt2
work/_opt1/work_decoder15_test_v_fast.asm
work/_opt1/work_decoder15_test_v_fast.dt2
work/_opt1/work__info
work/_opt1/_deps
work/_opt2
work/_opt2/work_decoder15_fast.asm
work/_opt2/work_decoder15_fast.dt2
work/_opt2/work_glbl_fast.asm
work/_opt2/work_glbl_fast.dt2
work/_opt2/work__info
work/_opt2/_deps
work/_temp
decoder15.v
decoder15.udo
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