文件名称:gcd
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文件大小:304.98kb
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这是一个求最大公约数的verilog源码-this is a verilog source code which can count the greatest common divider .
相关搜索: gcd_testbench
Verilog gcd
(系统自动生成,下载前可以参看下载内容)
下载文件列表
gcd/src/csrc/5NrIB_d.o
gcd/src/csrc/5NrI_d.o
gcd/src/csrc/5NrI_d.o.incr
gcd/src/csrc/BzDP_1_d.o
gcd/src/csrc/BzDP_1_d.o.incr
gcd/src/csrc/BzDP_1_l.dat
gcd/src/csrc/filelist
gcd/src/csrc/idincr.db
gcd/src/csrc/Makefile
gcd/src/csrc/product_timestamp
gcd/src/csrc/SIM_l.o
gcd/src/csrc/vcsconst.incr
gcd/src/csrc/vcspieces.incr
gcd/src/csrc/vcstype.incr
gcd/src/DVEfiles/dve_gui.log
gcd/src/DVEfiles/dve_history.log
gcd/src/DVEfiles/session.tcl
gcd/src/gcd_controller.v
gcd/src/gcd_controller.v~
gcd/src/gcd_datapath.v
gcd/src/gcd_datapath.v~
gcd/src/gcd_input_data
gcd/src/gcd_testbench.v
gcd/src/gcd_testbench.v~
gcd/src/gcd_test_output
gcd/src/gcd_top.v
gcd/src/gcd_top.v~
gcd/src/log
gcd/src/simv
gcd/src/simv.daidir/.version
gcd/src/simv.daidir/2N5hNe_1.db
gcd/src/simv.daidir/3CjfEb_1.db
gcd/src/simv.daidir/5NrI.tt
gcd/src/simv.daidir/AllModulesSkeletons.db
gcd/src/simv.daidir/b9dpyc_1.db
gcd/src/simv.daidir/BzDP_1.tt
gcd/src/simv.daidir/covg_defs
gcd/src/simv.daidir/didmap.db
gcd/src/simv.daidir/dve_filelist.db
gcd/src/simv.daidir/dve_macro.db
gcd/src/simv.daidir/external_functions
gcd/src/simv.daidir/heZTHe_1.db
gcd/src/simv.daidir/modfilename.db
gcd/src/simv.daidir/mUldHc_1.db
gcd/src/simv.daidir/nCDh3c_1.db
gcd/src/simv.daidir/offfilename.db
gcd/src/simv.daidir/RRrKjd_1.db
gcd/src/simv.daidir/SmwM2c_1.db
gcd/src/simv.daidir/str.db
gcd/src/simv.daidir/topmodules
gcd/src/simv.daidir/vcs_rebuild
gcd/src/ucli.key
gcd/src/vcs.key
gcd/syn/.synopsys_dc.setup
gcd/syn/.vcsmx_rebuild
gcd/syn/command.log
gcd/syn/default.svf
gcd/syn/EDFF-verilog-verilog.syn
gcd/syn/EDFF-verilog.pvl
gcd/syn/EDFF-verilog.syn
gcd/syn/EDFF.mr
gcd/syn/filenames.log
gcd/syn/gcd_controller-verilog-verilog.syn
gcd/syn/gcd_controller-verilog.pvl
gcd/syn/gcd_controller-verilog.syn
gcd/syn/GCD_CONTROLLER.mr
gcd/syn/gcd_datapath-verilog-verilog.syn
gcd/syn/gcd_datapath-verilog.pvl
gcd/syn/gcd_datapath-verilog.syn
gcd/syn/GCD_DATAPATH.mr
gcd/syn/gcd_testbench-verilog-verilog.syn
gcd/syn/gcd_testbench-verilog.pvl
gcd/syn/gcd_testbench-verilog.syn
gcd/syn/GCD_TESTBENCH.mr
gcd/syn/gcd_top-verilog-verilog.syn
gcd/syn/gcd_top-verilog.pvl
gcd/syn/gcd_top-verilog.syn
gcd/syn/GCD_TOP.mr
gcd/syn/Mux2-verilog-verilog.syn
gcd/syn/Mux2-verilog.pvl
gcd/syn/Mux2-verilog.syn
gcd/syn/MUX2.mr
gcd/syn/Mux3-verilog-verilog.syn
gcd/syn/Mux3-verilog.pvl
gcd/syn/Mux3-verilog.syn
gcd/syn/MUX3.mr
gcd/syn/REDFF-verilog-verilog.syn
gcd/syn/REDFF-verilog.pvl
gcd/syn/REDFF-verilog.syn
gcd/syn/REDFF.mr
gcd/src/csrc
gcd/src/DVEfiles
gcd/src/simv.daidir
gcd/syn/log
gcd/syn/mapped_db
gcd/syn/netlist
gcd/syn/script
gcd/syn/unmapped_db
gcd/sim
gcd/src
gcd/syn
gcd
gcd/src/csrc/5NrI_d.o
gcd/src/csrc/5NrI_d.o.incr
gcd/src/csrc/BzDP_1_d.o
gcd/src/csrc/BzDP_1_d.o.incr
gcd/src/csrc/BzDP_1_l.dat
gcd/src/csrc/filelist
gcd/src/csrc/idincr.db
gcd/src/csrc/Makefile
gcd/src/csrc/product_timestamp
gcd/src/csrc/SIM_l.o
gcd/src/csrc/vcsconst.incr
gcd/src/csrc/vcspieces.incr
gcd/src/csrc/vcstype.incr
gcd/src/DVEfiles/dve_gui.log
gcd/src/DVEfiles/dve_history.log
gcd/src/DVEfiles/session.tcl
gcd/src/gcd_controller.v
gcd/src/gcd_controller.v~
gcd/src/gcd_datapath.v
gcd/src/gcd_datapath.v~
gcd/src/gcd_input_data
gcd/src/gcd_testbench.v
gcd/src/gcd_testbench.v~
gcd/src/gcd_test_output
gcd/src/gcd_top.v
gcd/src/gcd_top.v~
gcd/src/log
gcd/src/simv
gcd/src/simv.daidir/.version
gcd/src/simv.daidir/2N5hNe_1.db
gcd/src/simv.daidir/3CjfEb_1.db
gcd/src/simv.daidir/5NrI.tt
gcd/src/simv.daidir/AllModulesSkeletons.db
gcd/src/simv.daidir/b9dpyc_1.db
gcd/src/simv.daidir/BzDP_1.tt
gcd/src/simv.daidir/covg_defs
gcd/src/simv.daidir/didmap.db
gcd/src/simv.daidir/dve_filelist.db
gcd/src/simv.daidir/dve_macro.db
gcd/src/simv.daidir/external_functions
gcd/src/simv.daidir/heZTHe_1.db
gcd/src/simv.daidir/modfilename.db
gcd/src/simv.daidir/mUldHc_1.db
gcd/src/simv.daidir/nCDh3c_1.db
gcd/src/simv.daidir/offfilename.db
gcd/src/simv.daidir/RRrKjd_1.db
gcd/src/simv.daidir/SmwM2c_1.db
gcd/src/simv.daidir/str.db
gcd/src/simv.daidir/topmodules
gcd/src/simv.daidir/vcs_rebuild
gcd/src/ucli.key
gcd/src/vcs.key
gcd/syn/.synopsys_dc.setup
gcd/syn/.vcsmx_rebuild
gcd/syn/command.log
gcd/syn/default.svf
gcd/syn/EDFF-verilog-verilog.syn
gcd/syn/EDFF-verilog.pvl
gcd/syn/EDFF-verilog.syn
gcd/syn/EDFF.mr
gcd/syn/filenames.log
gcd/syn/gcd_controller-verilog-verilog.syn
gcd/syn/gcd_controller-verilog.pvl
gcd/syn/gcd_controller-verilog.syn
gcd/syn/GCD_CONTROLLER.mr
gcd/syn/gcd_datapath-verilog-verilog.syn
gcd/syn/gcd_datapath-verilog.pvl
gcd/syn/gcd_datapath-verilog.syn
gcd/syn/GCD_DATAPATH.mr
gcd/syn/gcd_testbench-verilog-verilog.syn
gcd/syn/gcd_testbench-verilog.pvl
gcd/syn/gcd_testbench-verilog.syn
gcd/syn/GCD_TESTBENCH.mr
gcd/syn/gcd_top-verilog-verilog.syn
gcd/syn/gcd_top-verilog.pvl
gcd/syn/gcd_top-verilog.syn
gcd/syn/GCD_TOP.mr
gcd/syn/Mux2-verilog-verilog.syn
gcd/syn/Mux2-verilog.pvl
gcd/syn/Mux2-verilog.syn
gcd/syn/MUX2.mr
gcd/syn/Mux3-verilog-verilog.syn
gcd/syn/Mux3-verilog.pvl
gcd/syn/Mux3-verilog.syn
gcd/syn/MUX3.mr
gcd/syn/REDFF-verilog-verilog.syn
gcd/syn/REDFF-verilog.pvl
gcd/syn/REDFF-verilog.syn
gcd/syn/REDFF.mr
gcd/src/csrc
gcd/src/DVEfiles
gcd/src/simv.daidir
gcd/syn/log
gcd/syn/mapped_db
gcd/syn/netlist
gcd/syn/script
gcd/syn/unmapped_db
gcd/sim
gcd/src
gcd/syn
gcd
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