文件名称:UART
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- 上传时间：2012-10-26
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文件大小：248.25kb
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介绍说明－－下载内容来自于网络，使用问题请自行百度
自己实用Verilog编写的UART程序，1位开始位，8位数据位，1位停止位，本测试程序配置完管脚后，实用串口大师发送数据，则返回数据为发送数据+1-Verilog prepared their own UART practical procedures to start a bit, 8 data bits, 1 stop bit, the test procedure End pin configuration, the utility serial Master to send data, send data back data+1
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下载文件列表
UART/UART.prj
UART/synthesis/.recordref
UART/synthesis/stdout.log
UART/synthesis/traplog.tlg
UART/synthesis/uart_test.areasrr
UART/synthesis/uart_test.edn
UART/synthesis/uart_test.fse
UART/synthesis/uart_test.map
UART/synthesis/uart_test.sdf
UART/synthesis/uart_test.srd
UART/synthesis/uart_test.srm
UART/synthesis/uart_test.srr
UART/synthesis/uart_test.srs
UART/synthesis/uart_test.tlg
UART/synthesis/uart_test_sdc.sdc
UART/synthesis/uart_test_syn.prd
UART/synthesis/uart_test_syn.prj
UART/synthesis/syntmp/sap.log
UART/synthesis/syntmp/uart_test.msg
UART/synthesis/syntmp/uart_test.plg
UART/synthesis/syntmp
UART/synthesis
UART/simulation/meminit.dat
UART/simulation/modelsim.ini
UART/simulation/modelsim.ini.sav
UART/simulation
UART/hdl/rec.v
UART/hdl/send.v
UART/hdl/uart_test.v
UART/hdl
UART/designer/impl1/designer.log
UART/designer/impl1/uart_test.adb
UART/designer/impl1/uart_test.ide_des
UART/designer/impl1/uart_test.stp
UART/designer/impl1/uart_test.tcl
UART/designer/impl1/uart_test.dtf/verify.log
UART/designer/impl1/uart_test.dtf
UART/designer/impl1
UART/designer
UART
UART/synthesis/.recordref
UART/synthesis/stdout.log
UART/synthesis/traplog.tlg
UART/synthesis/uart_test.areasrr
UART/synthesis/uart_test.edn
UART/synthesis/uart_test.fse
UART/synthesis/uart_test.map
UART/synthesis/uart_test.sdf
UART/synthesis/uart_test.srd
UART/synthesis/uart_test.srm
UART/synthesis/uart_test.srr
UART/synthesis/uart_test.srs
UART/synthesis/uart_test.tlg
UART/synthesis/uart_test_sdc.sdc
UART/synthesis/uart_test_syn.prd
UART/synthesis/uart_test_syn.prj
UART/synthesis/syntmp/sap.log
UART/synthesis/syntmp/uart_test.msg
UART/synthesis/syntmp/uart_test.plg
UART/synthesis/syntmp
UART/synthesis
UART/simulation/meminit.dat
UART/simulation/modelsim.ini
UART/simulation/modelsim.ini.sav
UART/simulation
UART/hdl/rec.v
UART/hdl/send.v
UART/hdl/uart_test.v
UART/hdl
UART/designer/impl1/designer.log
UART/designer/impl1/uart_test.adb
UART/designer/impl1/uart_test.ide_des
UART/designer/impl1/uart_test.stp
UART/designer/impl1/uart_test.tcl
UART/designer/impl1/uart_test.dtf/verify.log
UART/designer/impl1/uart_test.dtf
UART/designer/impl1
UART/designer
UART
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