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文件名称:cis_100dpi_dsp

  • 所属分类：
    VHDL编程
  • 标签属性：
    [PDF]
  • 上传时间：
    2012-10-28
  • 文件大小：
    2.93mb
  • 已下载：
    1次
  • 提 供 者：
    袁****
  • 相关连接：
    无
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程序实现了采用CIS+AD9822+FPGA的结构形式对人民币进行采集。然后把采集到得数据通过EMIF接口传送给DSP。已通过调试-Program implements the use of CIS+ AD9822+ FPGA structure in the form of the RMB is collected. Then the data collected was transmitted through the EMIF interface to the DSP. Has passed debug
相关搜索： ad9822 fpga dsp INTERFACE

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cis_100dpi_dsp/
cis_100dpi_dsp/cis_100dpi_dsp/
cis_100dpi_dsp/cis_100dpi_dsp/1.cfi
cis_100dpi_dsp/cis_100dpi_dsp/1.mcs
cis_100dpi_dsp/cis_100dpi_dsp/1.prm
cis_100dpi_dsp/cis_100dpi_dsp/arwz.log
cis_100dpi_dsp/cis_100dpi_dsp/blk_mem_gen_ds512.pdf
cis_100dpi_dsp/cis_100dpi_dsp/coregen.cgp
cis_100dpi_dsp/cis_100dpi_dsp/device_usage_statistics.html
cis_100dpi_dsp/cis_100dpi_dsp/ip.vhd
cis_100dpi_dsp/cis_100dpi_dsp/ip.xaw
cis_100dpi_dsp/cis_100dpi_dsp/ip_arwz.ucf
cis_100dpi_dsp/cis_100dpi_dsp/iseconfig/
cis_100dpi_dsp/cis_100dpi_dsp/iseconfig/main.xreport
cis_100dpi_dsp/cis_100dpi_dsp/iseconfig/ram1.projectmgr
cis_100dpi_dsp/cis_100dpi_dsp/main.bgn
cis_100dpi_dsp/cis_100dpi_dsp/main.bit
cis_100dpi_dsp/cis_100dpi_dsp/main.bld
cis_100dpi_dsp/cis_100dpi_dsp/main.cmd_log
cis_100dpi_dsp/cis_100dpi_dsp/main.drc
cis_100dpi_dsp/cis_100dpi_dsp/main.lso
cis_100dpi_dsp/cis_100dpi_dsp/main.ncd
cis_100dpi_dsp/cis_100dpi_dsp/main.ngc
cis_100dpi_dsp/cis_100dpi_dsp/main.ngd
cis_100dpi_dsp/cis_100dpi_dsp/main.ngr
cis_100dpi_dsp/cis_100dpi_dsp/main.pad
cis_100dpi_dsp/cis_100dpi_dsp/main.par
cis_100dpi_dsp/cis_100dpi_dsp/main.pcf
cis_100dpi_dsp/cis_100dpi_dsp/main.prj
cis_100dpi_dsp/cis_100dpi_dsp/main.ptwx
cis_100dpi_dsp/cis_100dpi_dsp/main.stx
cis_100dpi_dsp/cis_100dpi_dsp/main.syr
cis_100dpi_dsp/cis_100dpi_dsp/main.twr
cis_100dpi_dsp/cis_100dpi_dsp/main.twx
cis_100dpi_dsp/cis_100dpi_dsp/main.ucf
cis_100dpi_dsp/cis_100dpi_dsp/main.unroutes
cis_100dpi_dsp/cis_100dpi_dsp/main.ut
cis_100dpi_dsp/cis_100dpi_dsp/main.xpi
cis_100dpi_dsp/cis_100dpi_dsp/main.xst
cis_100dpi_dsp/cis_100dpi_dsp/main_bitgen.xwbt
cis_100dpi_dsp/cis_100dpi_dsp/main_envsettings.html
cis_100dpi_dsp/cis_100dpi_dsp/main_guide.ncd
cis_100dpi_dsp/cis_100dpi_dsp/main_map.map
cis_100dpi_dsp/cis_100dpi_dsp/main_map.mrp
cis_100dpi_dsp/cis_100dpi_dsp/main_map.ncd
cis_100dpi_dsp/cis_100dpi_dsp/main_map.ngm
cis_100dpi_dsp/cis_100dpi_dsp/main_map.xrpt
cis_100dpi_dsp/cis_100dpi_dsp/main_ngdbuild.xrpt
cis_100dpi_dsp/cis_100dpi_dsp/main_pad.csv
cis_100dpi_dsp/cis_100dpi_dsp/main_pad.txt
cis_100dpi_dsp/cis_100dpi_dsp/main_par.xrpt
cis_100dpi_dsp/cis_100dpi_dsp/main_prev_built.ngd
cis_100dpi_dsp/cis_100dpi_dsp/main_summary.html
cis_100dpi_dsp/cis_100dpi_dsp/main_summary.xml
cis_100dpi_dsp/cis_100dpi_dsp/main_usage.xml
cis_100dpi_dsp/cis_100dpi_dsp/main_vhdl.prj
cis_100dpi_dsp/cis_100dpi_dsp/main_xst.xrpt
cis_100dpi_dsp/cis_100dpi_dsp/mian.vhd
cis_100dpi_dsp/cis_100dpi_dsp/ram1.gise
cis_100dpi_dsp/cis_100dpi_dsp/ram1.ntrc_log
cis_100dpi_dsp/cis_100dpi_dsp/ram1.restore
cis_100dpi_dsp/cis_100dpi_dsp/ram1.xise
cis_100dpi_dsp/cis_100dpi_dsp/ram1_ise12migration.zip
cis_100dpi_dsp/cis_100dpi_dsp/ram1_xdb/
cis_100dpi_dsp/cis_100dpi_dsp/ram1_xdb/cst.xbcd
cis_100dpi_dsp/cis_100dpi_dsp/ram1_xdb/tmp/
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip.asy
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip.ngc
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip.sym
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip.v
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip.veo
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip.vhd
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip.vho
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip.xco
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip_blk_mem_gen_v2_7_xst_1.ngc_xst.xrpt
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip_flist.txt
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip_readme.txt
cis_100dpi_dsp/cis_100dpi_dsp/ram_ip_xmdf.tcl
cis_100dpi_dsp/cis_100dpi_dsp/templates/
cis_100dpi_dsp/cis_100dpi_dsp/templates/coregen.xml
cis_100dpi_dsp/cis_100dpi_dsp/test.txt
cis_100dpi_dsp/cis_100dpi_dsp/tmp/
cis_100dpi_dsp/cis_100dpi_dsp/tmp/_cg/
cis_100dpi_dsp/cis_100dpi_dsp/Untitled.cfi
cis_100dpi_dsp/cis_100dpi_dsp/Untitled.mcs
cis_100dpi_dsp/cis_100dpi_dsp/Untitled.prm
cis_100dpi_dsp/cis_100dpi_dsp/usage_statistics_webtalk.html
cis_100dpi_dsp/cis_100dpi_dsp/webtalk.log
cis_100dpi_dsp/cis_100dpi_dsp/webtalk_pn.xml
cis_100dpi_dsp/cis_100dpi_dsp/xaw2vhdl.log
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0.ise
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/cst.xbcd
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise.lock
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/version
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/Autonym/
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/common/
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/STE/
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/__OBJSTORE__/_ProjRepoInternal_/
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/__REGISTRY__/
cis_100dpi_dsp/cis_100dpi_dsp/xlnx_auto_0_xdb/tmp/ise/__REGISTRY

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