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文件名称:generic_fifos

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  • 上传时间:
    2012-10-31
  • 文件大小:
    39.19kb
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Generic FIFO for use with both xilinx and altera
相关搜索: altera fifo

(系统自动生成,下载前可以参看下载内容)

下载文件列表

generic_fifos/bench/CVS/Entries
generic_fifos/bench/CVS/Repository
generic_fifos/bench/CVS/Root
generic_fifos/bench/verilog/CVS/Entries
generic_fifos/bench/verilog/CVS/Repository
generic_fifos/bench/verilog/CVS/Root
generic_fifos/bench/verilog/test_bench_top.v
generic_fifos/CVS/Entries
generic_fifos/CVS/Repository
generic_fifos/CVS/Root
generic_fifos/doc/CVS/Entries
generic_fifos/doc/CVS/Repository
generic_fifos/doc/CVS/Root
generic_fifos/doc/README.txt
generic_fifos/oc8051_dptr.v
generic_fifos/risc16f84_clk2x.v
generic_fifos/rtl/CVS/Entries
generic_fifos/rtl/CVS/Repository
generic_fifos/rtl/CVS/Root
generic_fifos/rtl/verilog/CVS/Entries
generic_fifos/rtl/verilog/CVS/Repository
generic_fifos/rtl/verilog/CVS/Root
generic_fifos/rtl/verilog/generic_fifo_dc.v
generic_fifos/rtl/verilog/generic_fifo_dc_gray.v
generic_fifos/rtl/verilog/generic_fifo_lfsr.v
generic_fifos/rtl/verilog/generic_fifo_sc_a.v
generic_fifos/rtl/verilog/generic_fifo_sc_b.v
generic_fifos/rtl/verilog/lfsr.v
generic_fifos/rtl/verilog/timescale.v
generic_fifos/sim/CVS/Entries
generic_fifos/sim/CVS/Repository
generic_fifos/sim/CVS/Root
generic_fifos/sim/rtl_sim/bin/CVS/Entries
generic_fifos/sim/rtl_sim/bin/CVS/Repository
generic_fifos/sim/rtl_sim/bin/CVS/Root
generic_fifos/sim/rtl_sim/bin/Makefile
generic_fifos/sim/rtl_sim/CVS/Entries
generic_fifos/sim/rtl_sim/CVS/Repository
generic_fifos/sim/rtl_sim/CVS/Root
generic_fifos/sim/rtl_sim/run/CVS/Entries
generic_fifos/sim/rtl_sim/run/CVS/Repository
generic_fifos/sim/rtl_sim/run/CVS/Root
generic_fifos/sim/rtl_sim/run/waves/CVS/Entries
generic_fifos/sim/rtl_sim/run/waves/CVS/Repository
generic_fifos/sim/rtl_sim/run/waves/CVS/Root
generic_fifos/sim/rtl_sim/run/waves/waves.do
generic_fifos/usb1_fifo2.v
generic_fifos/sim/rtl_sim/run/waves/CVS
generic_fifos/sim/rtl_sim/bin/CVS
generic_fifos/sim/rtl_sim/run/CVS
generic_fifos/sim/rtl_sim/run/waves
generic_fifos/bench/verilog/CVS
generic_fifos/rtl/verilog/CVS
generic_fifos/sim/rtl_sim/bin
generic_fifos/sim/rtl_sim/CVS
generic_fifos/sim/rtl_sim/run
generic_fifos/bench/CVS
generic_fifos/bench/verilog
generic_fifos/doc/CVS
generic_fifos/rtl/CVS
generic_fifos/rtl/verilog
generic_fifos/sim/CVS
generic_fifos/sim/rtl_sim
generic_fifos/bench
generic_fifos/CVS
generic_fifos/doc
generic_fifos/rtl
generic_fifos/sim
generic_fifos

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