设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component:　FIFO control

　　　logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the

　　 RAM so that the first data word written into the RAM is also the first data word retrieved

　　 from the RAM. As shown in the Figure 1, the RAM is implemented to operate as a FIFO. The

　　 RAM is assumed to have separate data inputs and outputs, an N-bit address bus (ADD) and an

　　 active high write enable (WE). The inputs to FIFO/Stack include PUSH, POP, INIT (all

　　 active high) in addition to the rising edge triggered CLK input. The FIFO logic will not only

　　 supply the address and write enable to the RAM, but will also supply active high flags for

　　 FULL, EMPTY, NOPOP, and NOPUSH conditions.