文件名称:ddrsdram_verilog
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- 上传时间:2012-11-04
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文件大小:734.49kb
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内附doc是DDR SDRAM 参考设计文档;model包含SDRAM Verilog的模型;simulation包含verilog测试平台、modelsim工程文、设计库函数;source包含verilog源文件;synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with verilog test platform, modelsim project text, design library function source contains the verilog source files synthesis comprehensive document that contains the project.
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下载文件列表
model/mt46v4m16.v
route/ddr_sdram.csf
route/ddr_sdram.esf
route/ddr_sdram.psf
route/ddr_sdram.quartus
route/ddr_sdram.vqm
route/pll1.v
simulation/ddr_compile_all.v
simulation/ddr_sdram_tb.v
simulation/modelsim.ini
simulation/readme.txt
simulation/work/altclklock/verilog.psm
simulation/work/altclklock/_primary.dat
simulation/work/altclklock/_primary.vhd
simulation/work/ddr_command/verilog.psm
simulation/work/ddr_command/_primary.dat
simulation/work/ddr_command/_primary.vhd
simulation/work/ddr_control_interface/verilog.psm
simulation/work/ddr_control_interface/_primary.dat
simulation/work/ddr_control_interface/_primary.vhd
simulation/work/ddr_data_path/verilog.psm
simulation/work/ddr_data_path/_primary.dat
simulation/work/ddr_data_path/_primary.vhd
simulation/work/ddr_sdram/verilog.psm
simulation/work/ddr_sdram/_primary.dat
simulation/work/ddr_sdram/_primary.vhd
simulation/work/ddr_sdram_tb/verilog.psm
simulation/work/ddr_sdram_tb/_primary.dat
simulation/work/ddr_sdram_tb/_primary.vhd
simulation/work/mt46v4m16/verilog.psm
simulation/work/mt46v4m16/_primary.dat
simulation/work/mt46v4m16/_primary.vhd
simulation/work/pll1/verilog.psm
simulation/work/pll1/_primary.dat
simulation/work/pll1/_primary.vhd
simulation/work/_info
source/altclklock.v
source/ddr_Command.v
source/ddr_control_interface.v
source/ddr_data_path.v
source/ddr_sdram.v
source/Params.v
source/pll1.v
synthesis/synplicity/ddr_data_path.srm
synthesis/synplicity/ddr_data_path.srr
synthesis/synplicity/ddr_data_path.srs
synthesis/synplicity/ddr_data_path.tlg
synthesis/synplicity/ddr_data_path.xrf
synthesis/synplicity/ddr_sdram.prj
synthesis/synplicity/ddr_sdram.sdc
synthesis/synplicity/ddr_sdram.srm
synthesis/synplicity/ddr_sdram.srr
synthesis/synplicity/ddr_sdram.srs
synthesis/synplicity/ddr_sdram.tcl
synthesis/synplicity/ddr_sdram.tlg
synthesis/synplicity/ddr_sdram.vqm
synthesis/synplicity/ddr_sdram.xrf
synthesis/synplicity/ddr_sdram_cons.tcl
synthesis/synplicity/ddr_sdram_rm.tcl
doc/ddr_sdram.pdf
simulation/work/altclklock
simulation/work/ddr_command
simulation/work/ddr_control_interface
simulation/work/ddr_data_path
simulation/work/ddr_sdram
simulation/work/ddr_sdram_tb
simulation/work/mt46v4m16
simulation/work/pll1
simulation/work
synthesis/synplicity
model
route
simulation
source
synthesis
doc
route/ddr_sdram.csf
route/ddr_sdram.esf
route/ddr_sdram.psf
route/ddr_sdram.quartus
route/ddr_sdram.vqm
route/pll1.v
simulation/ddr_compile_all.v
simulation/ddr_sdram_tb.v
simulation/modelsim.ini
simulation/readme.txt
simulation/work/altclklock/verilog.psm
simulation/work/altclklock/_primary.dat
simulation/work/altclklock/_primary.vhd
simulation/work/ddr_command/verilog.psm
simulation/work/ddr_command/_primary.dat
simulation/work/ddr_command/_primary.vhd
simulation/work/ddr_control_interface/verilog.psm
simulation/work/ddr_control_interface/_primary.dat
simulation/work/ddr_control_interface/_primary.vhd
simulation/work/ddr_data_path/verilog.psm
simulation/work/ddr_data_path/_primary.dat
simulation/work/ddr_data_path/_primary.vhd
simulation/work/ddr_sdram/verilog.psm
simulation/work/ddr_sdram/_primary.dat
simulation/work/ddr_sdram/_primary.vhd
simulation/work/ddr_sdram_tb/verilog.psm
simulation/work/ddr_sdram_tb/_primary.dat
simulation/work/ddr_sdram_tb/_primary.vhd
simulation/work/mt46v4m16/verilog.psm
simulation/work/mt46v4m16/_primary.dat
simulation/work/mt46v4m16/_primary.vhd
simulation/work/pll1/verilog.psm
simulation/work/pll1/_primary.dat
simulation/work/pll1/_primary.vhd
simulation/work/_info
source/altclklock.v
source/ddr_Command.v
source/ddr_control_interface.v
source/ddr_data_path.v
source/ddr_sdram.v
source/Params.v
source/pll1.v
synthesis/synplicity/ddr_data_path.srm
synthesis/synplicity/ddr_data_path.srr
synthesis/synplicity/ddr_data_path.srs
synthesis/synplicity/ddr_data_path.tlg
synthesis/synplicity/ddr_data_path.xrf
synthesis/synplicity/ddr_sdram.prj
synthesis/synplicity/ddr_sdram.sdc
synthesis/synplicity/ddr_sdram.srm
synthesis/synplicity/ddr_sdram.srr
synthesis/synplicity/ddr_sdram.srs
synthesis/synplicity/ddr_sdram.tcl
synthesis/synplicity/ddr_sdram.tlg
synthesis/synplicity/ddr_sdram.vqm
synthesis/synplicity/ddr_sdram.xrf
synthesis/synplicity/ddr_sdram_cons.tcl
synthesis/synplicity/ddr_sdram_rm.tcl
doc/ddr_sdram.pdf
simulation/work/altclklock
simulation/work/ddr_command
simulation/work/ddr_control_interface
simulation/work/ddr_data_path
simulation/work/ddr_sdram
simulation/work/ddr_sdram_tb
simulation/work/mt46v4m16
simulation/work/pll1
simulation/work
synthesis/synplicity
model
route
simulation
source
synthesis
doc
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