文件名称:VHDL2
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序列信号发生器:
在系统时钟的作用下能够循环产生一组或多组序列信号的时序电路,(循环产生一组序列信号0111010011011010)
序列检测器:
检测一组或多组又二进制码组成的脉冲序列信号,当序列检测器连续收到一组或多组序列信号,如果与预先设置的码11010相同的时候,输出1,否则输出0.
-Sequence of signal generator: the role of the system clock cycle to generate one or more signal timing sequence circuit (cycle to generate a sequence signal 0111010011011010) sequence detector: detecting one or more group was composed of binary code pulses sequence of signal detection when the sequence of one or more groups received a continuous sequence of signals, if the pre-set code 11010 with the same time, output 1, otherwise output 0.
在系统时钟的作用下能够循环产生一组或多组序列信号的时序电路,(循环产生一组序列信号0111010011011010)
序列检测器:
检测一组或多组又二进制码组成的脉冲序列信号,当序列检测器连续收到一组或多组序列信号,如果与预先设置的码11010相同的时候,输出1,否则输出0.
-Sequence of signal generator: the role of the system clock cycle to generate one or more signal timing sequence circuit (cycle to generate a sequence signal 0111010011011010) sequence detector: detecting one or more group was composed of binary code pulses sequence of signal detection when the sequence of one or more groups received a continuous sequence of signals, if the pre-set code 11010 with the same time, output 1, otherwise output 0.
相关搜索: detection of pulses
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EDA实验报告实验三:序列信号发生器与检测器设计.docx
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