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文件名称:VERILOG-jpeg

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  • 上传时间:
    2012-11-07
  • 文件大小:
    101.32kb
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    8次
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介绍说明--下载内容来自于网络,使用问题请自行百度

用Verilog语言在FPGA上实现JPEG图片的解码,附带testbench-With the Verilog language in the FPGA to achieve JPEG image decoding, with testbench
(系统自动生成,下载前可以参看下载内容)

下载文件列表

VERILOG-jpeg/dct/dct.v
VERILOG-jpeg/dct/dctu.v
VERILOG-jpeg/dct/dctub.v
VERILOG-jpeg/dct/dct_bench/bench_top.v
VERILOG-jpeg/dct/dct_cos_table.v
VERILOG-jpeg/dct/dct_mac.v
VERILOG-jpeg/dct/dct_syn.v
VERILOG-jpeg/dct/fdct.v
VERILOG-jpeg/dct/huffman/bench/bench_top.v
VERILOG-jpeg/dct/huffman/bench/generic_dpram.v
VERILOG-jpeg/dct/huffman/bench/generic_fifo_lfsr.v
VERILOG-jpeg/dct/huffman/bench/lfsr.v
VERILOG-jpeg/dct/huffman/bench/timescale.v
VERILOG-jpeg/dct/huffman/huffman_dec.v
VERILOG-jpeg/dct/huffman/huffman_enc.v
VERILOG-jpeg/dct/huffman/huffman_tables.v
VERILOG-jpeg/dct/ro_cnt.v
VERILOG-jpeg/dct/rtl_sim/Makefile.txt
VERILOG-jpeg/dct/ud_cnt.v
VERILOG-jpeg/dct/zigzag.v
VERILOG-jpeg/jpeg/bench_top/jpeg_encoder.v
VERILOG-jpeg/jpeg/jpeg_encoder.v
VERILOG-jpeg/jpeg/sim/cds.lib
VERILOG-jpeg/jpeg/sim/hdl.var
VERILOG-jpeg/jpeg/sim/Makefile.txt
VERILOG-jpeg/qnr/attic/div.v
VERILOG-jpeg/qnr/attic/div_us.v
VERILOG-jpeg/qnr/attic/ro_cnt.v
VERILOG-jpeg/qnr/attic/ud_cnt.v
VERILOG-jpeg/qnr/bench/bench_div_top.v
VERILOG-jpeg/qnr/bench/bench_qnr_top.v
VERILOG-jpeg/qnr/bench/timescale.v
VERILOG-jpeg/qnr/div_su.v
VERILOG-jpeg/qnr/div_uu.v
VERILOG-jpeg/qnr/jpeg_qnr.v
VERILOG-jpeg/rgb2ycrcb/modelsim.ini
VERILOG-jpeg/rgb2ycrcb/rgb2ycrcb/_info
VERILOG-jpeg/rgb2ycrcb/rgb2ycrcb.mpf
VERILOG-jpeg/rgb2ycrcb/rgb2ycrcb.v
VERILOG-jpeg/rgb2ycrcb/rgb2ycrcb_testbench.v
VERILOG-jpeg/rgb2ycrcb/rgb2ycrcb_webAddress.txt
VERILOG-jpeg/rgb2ycrcb/tcl_stacktrace.txt
VERILOG-jpeg/rgb2ycrcb/transcript
VERILOG-jpeg/rgb2ycrcb/work/_info
VERILOG-jpeg/run_length_coding/attic/jpeg_rle2.v
VERILOG-jpeg/run_length_coding/bench/bench.v.txt
VERILOG-jpeg/run_length_coding/jpeg_rle.v
VERILOG-jpeg/run_length_coding/jpeg_rle1.v
VERILOG-jpeg/run_length_coding/jpeg_rzs.v
VERILOG-jpeg/dct/huffman/bench
VERILOG-jpeg/dct/dct_bench
VERILOG-jpeg/dct/huffman
VERILOG-jpeg/dct/rtl_sim
VERILOG-jpeg/jpeg/bench_top
VERILOG-jpeg/jpeg/sim
VERILOG-jpeg/qnr/attic
VERILOG-jpeg/qnr/bench
VERILOG-jpeg/rgb2ycrcb/rgb2ycrcb
VERILOG-jpeg/rgb2ycrcb/work
VERILOG-jpeg/run_length_coding/attic
VERILOG-jpeg/run_length_coding/bench
VERILOG-jpeg/dct
VERILOG-jpeg/jpeg
VERILOG-jpeg/qnr
VERILOG-jpeg/rgb2ycrcb
VERILOG-jpeg/run_length_coding
VERILOG-jpeg

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