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文件名称:UART

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  • 上传时间:
    2012-11-07
  • 文件大小:
    1.37mb
  • 已下载:
    3次
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    别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容来自于网络,使用问题请自行百度

使用Quartus ii软件,编程语言为Verilog语言,实现UART通信协议,FPGA的时钟信号为50MHz-Using the Quartus ii software, programming languages Verilog, UART communication protocol implementation, FPGA 50MHz clock signal
(系统自动生成,下载前可以参看下载内容)

下载文件列表

UART/db/mytest.(0).cnf.cdb
UART/db/mytest.(0).cnf.hdb
UART/db/mytest.asm.qmsg
UART/db/mytest.asm_labs.ddb
UART/db/mytest.cbx.xml
UART/db/mytest.cmp.bpm
UART/db/mytest.cmp.cdb
UART/db/mytest.cmp.ecobp
UART/db/mytest.cmp.hdb
UART/db/mytest.cmp.kpt
UART/db/mytest.cmp.logdb
UART/db/mytest.cmp.rdb
UART/db/mytest.cmp_merge.kpt
UART/db/mytest.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
UART/db/mytest.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
UART/db/mytest.db_info
UART/db/mytest.eco.cdb
UART/db/mytest.eds_overflow
UART/db/mytest.fit.qmsg
UART/db/mytest.hier_info
UART/db/mytest.hif
UART/db/mytest.lpc.html
UART/db/mytest.lpc.rdb
UART/db/mytest.lpc.txt
UART/db/mytest.map.bpm
UART/db/mytest.map.cdb
UART/db/mytest.map.ecobp
UART/db/mytest.map.hdb
UART/db/mytest.map.kpt
UART/db/mytest.map.logdb
UART/db/mytest.map.qmsg
UART/db/mytest.map_bb.cdb
UART/db/mytest.map_bb.hdb
UART/db/mytest.map_bb.logdb
UART/db/mytest.pre_map.cdb
UART/db/mytest.pre_map.hdb
UART/db/mytest.rtlv.hdb
UART/db/mytest.rtlv_sg.cdb
UART/db/mytest.rtlv_sg_swap.cdb
UART/db/mytest.sgdiff.cdb
UART/db/mytest.sgdiff.hdb
UART/db/mytest.sim.cvwf
UART/db/mytest.sim.hdb
UART/db/mytest.sim.qmsg
UART/db/mytest.sim.rdb
UART/db/mytest.sld_design_entry.sci
UART/db/mytest.sld_design_entry_dsc.sci
UART/db/mytest.sta.qmsg
UART/db/mytest.sta.rdb
UART/db/mytest.sta_cmp.8_slow_1200mv_85c.tdb
UART/db/mytest.syn_hier_info
UART/db/mytest.tiscmp.fast_1200mv_0c.ddb
UART/db/mytest.tiscmp.slow_1200mv_0c.ddb
UART/db/mytest.tiscmp.slow_1200mv_85c.ddb
UART/db/mytest.tis_db_list.ddb
UART/db/mytest.tmw_info
UART/db/prev_cmp_mytest.asm.qmsg
UART/db/prev_cmp_mytest.fit.qmsg
UART/db/prev_cmp_mytest.map.qmsg
UART/db/prev_cmp_mytest.qmsg
UART/db/prev_cmp_mytest.sim.qmsg
UART/db/prev_cmp_mytest.sta.qmsg
UART/db/wed.wsf
UART/incremental_db/compiled_partitions/mytest.root_partition.cmp.atm
UART/incremental_db/compiled_partitions/mytest.root_partition.cmp.dfp
UART/incremental_db/compiled_partitions/mytest.root_partition.cmp.hdbx
UART/incremental_db/compiled_partitions/mytest.root_partition.cmp.kpt
UART/incremental_db/compiled_partitions/mytest.root_partition.cmp.logdb
UART/incremental_db/compiled_partitions/mytest.root_partition.cmp.rcf
UART/incremental_db/compiled_partitions/mytest.root_partition.map.atm
UART/incremental_db/compiled_partitions/mytest.root_partition.map.dpi
UART/incremental_db/compiled_partitions/mytest.root_partition.map.hdbx
UART/incremental_db/compiled_partitions/mytest.root_partition.map.kpt
UART/incremental_db/README
UART/mytest.asm.rpt
UART/mytest.done
UART/mytest.fit.rpt
UART/mytest.fit.smsg
UART/mytest.fit.summary
UART/mytest.flow.rpt
UART/mytest.map.rpt
UART/mytest.map.smsg
UART/mytest.map.summary
UART/mytest.pin
UART/mytest.qpf
UART/mytest.qsf
UART/mytest.qws
UART/mytest.sim.rpt
UART/mytest.sof
UART/mytest.sta.rpt
UART/mytest.sta.summary
UART/mytest.v
UART/mytest.v.bak
UART/mytest.vwf
UART/UART.vhd
UART/URAT.v
UART/incremental_db/compiled_partitions
UART/db
UART/incremental_db
UART

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