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文件名称:FlashROM

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [VHDL] [源码]
  • 上传时间：
    2012-11-08
  • 文件大小：
    386.02kb
  • 已下载：
    0次
  • 提 供 者：
    zho***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

actel fpga fusion kit 使用的flashrom操作-actel fpga fusion kit operation using flashrom
相关搜索： Actel FPGA

(系统自动生成,下载前可以参看下载内容)

下载文件列表

FlashROM实验/Source File/FlashROM_Out.v
FlashROM实验/Source File/Flash_ROM_Ctr.v
FlashROM实验/Source File/Flash_ROM_Top.v
FlashROM实验/Project/Flash_ROM/Flash_ROM.prj
FlashROM实验/Project/Flash_ROM/viewdraw/viewdraw.ini
FlashROM实验/Project/Flash_ROM/viewdraw/vf/project.lst
FlashROM实验/Project/Flash_ROM/synthesis/.recordref
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.areasrr
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.edn
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.fse
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.htm
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.map
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.sap
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.sdf
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.srd
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.srm
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.srr
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.srs
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16.tlg
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16_drc.rpt
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16_sdc.sdc
FlashROM实验/Project/Flash_ROM/synthesis/FlashROM16_syn.prj
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.areasrr
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.edn
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.fse
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.htm
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.map
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.sap
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.sdf
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.srd
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.srm
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.srr
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.srs
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top.tlg
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top_drc.rpt
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top_sdc.sdc
FlashROM实验/Project/Flash_ROM/synthesis/Flash_ROM_Top_syn.prj
FlashROM实验/Project/Flash_ROM/synthesis/stdout.log
FlashROM实验/Project/Flash_ROM/synthesis/traplog.tlg
FlashROM实验/Project/Flash_ROM/synthesis/syntmp/FlashROM16.msg
FlashROM实验/Project/Flash_ROM/synthesis/syntmp/FlashROM16.plg
FlashROM实验/Project/Flash_ROM/synthesis/syntmp/FlashROM16_flink.htm
FlashROM实验/Project/Flash_ROM/synthesis/syntmp/FlashROM16_srr.htm
FlashROM实验/Project/Flash_ROM/synthesis/syntmp/FlashROM16_toc.htm
FlashROM实验/Project/Flash_ROM/synthesis/syntmp/Flash_ROM_Top.msg
FlashROM实验/Project/Flash_ROM/synthesis/syntmp/Flash_ROM_Top.plg
FlashROM实验/Project/Flash_ROM/synthesis/syntmp/Flash_ROM_Top_flink.htm
FlashROM实验/Project/Flash_ROM/synthesis/syntmp/Flash_ROM_Top_srr.htm
FlashROM实验/Project/Flash_ROM/synthesis/syntmp/Flash_ROM_Top_toc.htm
FlashROM实验/Project/Flash_ROM/synthesis/syntmp/sap.log
FlashROM实验/Project/Flash_ROM/stimulus/BtimErrors.log
FlashROM实验/Project/Flash_ROM/stimulus/Flash_ROM_Top.dsk
FlashROM实验/Project/Flash_ROM/stimulus/Flash_ROM_Top.hpj
FlashROM实验/Project/Flash_ROM/stimulus/files_to_build.txt
FlashROM实验/Project/Flash_ROM/stimulus/waveperl.log
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16_work.ixf
FlashROM实验/Project/Flash_ROM/smartgen/smartgen.aws
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.cxf
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.gen
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.log
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.mem
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.ufc
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/FlashROM16.v
FlashROM实验/Project/Flash_ROM/smartgen/FlashROM16/hdlsynchk.tcl
FlashROM实验/Project/Flash_ROM/simulation/FlashROM16.mem
FlashROM实验/Project/Flash_ROM/simulation/meminit.dat
FlashROM实验/Project/Flash_ROM/simulation/modelsim.ini
FlashROM实验/Project/Flash_ROM/simulation/modelsim.ini.sav
FlashROM实验/Project/Flash_ROM/simulation/modelsim.log
FlashROM实验/Project/Flash_ROM/simulation/vsim.wlf
FlashROM实验/Project/Flash_ROM/simulation/presynth/_info
FlashROM实验/Project/Flash_ROM/simulation/presynth/testbench/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/testbench/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulation/presynth/testbench/verilog.psm
FlashROM实验/Project/Flash_ROM/simulation/presynth/tb_clock_minmax/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/tb_clock_minmax/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulation/presynth/tb_clock_minmax/verilog.psm
FlashROM实验/Project/Flash_ROM/simulation/presynth/stimulus/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/stimulus/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulation/presynth/stimulus/verilog.psm
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash_@r@o@m_@top/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash_@r@o@m_@top/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash_@r@o@m_@top/verilog.psm
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash_@r@o@m_@ctr/_primary.dat
FlashROM实验/Project/Flash_ROM/simulation/presynth/@flash_@r@o@m_@ctr/_primary.vhd
FlashROM实验/Project/Flash_ROM/simulati

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