文件名称:cnt8bc
介绍说明－－下载内容来自于网络，使用问题请自行百度
8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features:
The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered.
The counter is with an asynchronous reset that assigns a specific initial value for counting.
The counter is with a synchronous data load control input for a new value of counting and an enable control input for allowing the up and down counting. The load control input has a priority over the enable control input. This implies that when the load operation is in process the counter operation is prohibited.
Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER, may be used.
The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered.
The counter is with an asynchronous reset that assigns a specific initial value for counting.
The counter is with a synchronous data load control input for a new value of counting and an enable control input for allowing the up and down counting. The load control input has a priority over the enable control input. This implies that when the load operation is in process the counter operation is prohibited.
Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER, may be used.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
cnt8bc.txt
本网站为编程资源及源代码搜集、介绍的搜索网站，版权归原作者所有！ 粤ICP备11031372号
1999-2046 搜珍网 All Rights Reserved.