8位加减带异步复位计数器，使用双向输入管脚-　　Design an 8-bit up and down synchronous counter in VHDL with the following features:

The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered.

The counter is with an asynchronous reset that assigns a specific initial value for counting.

The counter is with a synchronous data load control input for a new value of counting and an enable control input for allowing the up and down counting. The load control input has a priority over the enable control input. This implies that when the load operation is in process the counter operation is prohibited.

Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER, may be used.