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文件名称:RISC-CPU

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-09
  • 文件大小：
    3mb
  • 已下载：
    1次
  • 提 供 者：
    v*****
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放在存储器初始文件中。

PS：为什么没有Verilog选项呢-A simple CPU, FPGA implementation to streamline the instruction set architecture, each instruction 16bit, high three operands for the instruction, the 13 address, the CPU can achieve the eight kinds of instruction operations, respectively, HLT (a medium-term empty) ADD (add operation) SKZ (zero skip) AND (phase operation) the XOR (exclusive OR operation) LDA (read data) STO (write data) JMP (unconditional jump instruction). cpu consists of eight parts, clock generator, the instruction register, accumulator, arithmetic logic unit, the data controller, the state controller, the program counter, the address multiplexer, the various components interoperate relations by the state controller to control, program instructions stored in the initial rom the routines stored in memory the initial file. PS: Why is there no Verilog options.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

RISC CPU/accum.v
RISC CPU/addr_decode.v
RISC CPU/adr.v
RISC CPU/altera_mf.v
RISC CPU/alu.v
RISC CPU/clk_gen.v
RISC CPU/counter.v
RISC CPU/CPU.asm.rpt
RISC CPU/CPU.done
RISC CPU/CPU.fit.rpt
RISC CPU/CPU.fit.smsg
RISC CPU/CPU.fit.summary
RISC CPU/CPU.flow.rpt
RISC CPU/CPU.map.rpt
RISC CPU/CPU.map.smsg
RISC CPU/CPU.map.summary
RISC CPU/CPU.pin
RISC CPU/CPU.pof
RISC CPU/CPU.qpf
RISC CPU/CPU.qsf
RISC CPU/CPU.qws
RISC CPU/CPU.sof
RISC CPU/CPU.tan.rpt
RISC CPU/CPU.vwf
RISC CPU/cpu_ram_1.hex
RISC CPU/cpu_ram_1.v
RISC CPU/cpu_ram_1.ver
RISC CPU/cpu_rom_1.hex
RISC CPU/cpu_rom_1.v
RISC CPU/cpu_rom_1.ver
RISC CPU/cpu_top.v
RISC CPU/cpu_tp.v
RISC CPU/datactl.v
RISC CPU/db/altsyncram_98d1.tdf
RISC CPU/db/altsyncram_s581.tdf
RISC CPU/db/CPU.(0).cnf.cdb
RISC CPU/db/CPU.(0).cnf.hdb
RISC CPU/db/CPU.(1).cnf.cdb
RISC CPU/db/CPU.(1).cnf.hdb
RISC CPU/db/CPU.(10).cnf.cdb
RISC CPU/db/CPU.(10).cnf.hdb
RISC CPU/db/CPU.(11).cnf.cdb
RISC CPU/db/CPU.(11).cnf.hdb
RISC CPU/db/CPU.(12).cnf.cdb
RISC CPU/db/CPU.(12).cnf.hdb
RISC CPU/db/CPU.(13).cnf.cdb
RISC CPU/db/CPU.(13).cnf.hdb
RISC CPU/db/CPU.(14).cnf.cdb
RISC CPU/db/CPU.(14).cnf.hdb
RISC CPU/db/CPU.(15).cnf.cdb
RISC CPU/db/CPU.(15).cnf.hdb
RISC CPU/db/CPU.(16).cnf.cdb
RISC CPU/db/CPU.(16).cnf.hdb
RISC CPU/db/CPU.(17).cnf.cdb
RISC CPU/db/CPU.(17).cnf.hdb
RISC CPU/db/CPU.(18).cnf.cdb
RISC CPU/db/CPU.(18).cnf.hdb
RISC CPU/db/CPU.(2).cnf.cdb
RISC CPU/db/CPU.(2).cnf.hdb
RISC CPU/db/CPU.(3).cnf.cdb
RISC CPU/db/CPU.(3).cnf.hdb
RISC CPU/db/CPU.(4).cnf.cdb
RISC CPU/db/CPU.(4).cnf.hdb
RISC CPU/db/CPU.(5).cnf.cdb
RISC CPU/db/CPU.(5).cnf.hdb
RISC CPU/db/CPU.(6).cnf.cdb
RISC CPU/db/CPU.(6).cnf.hdb
RISC CPU/db/CPU.(7).cnf.cdb
RISC CPU/db/CPU.(7).cnf.hdb
RISC CPU/db/CPU.(8).cnf.cdb
RISC CPU/db/CPU.(8).cnf.hdb
RISC CPU/db/CPU.(9).cnf.cdb
RISC CPU/db/CPU.(9).cnf.hdb
RISC CPU/db/CPU.asm.qmsg
RISC CPU/db/CPU.asm_labs.ddb
RISC CPU/db/CPU.cbx.xml
RISC CPU/db/CPU.cmp.bpm
RISC CPU/db/CPU.cmp.cdb
RISC CPU/db/CPU.cmp.ecobp
RISC CPU/db/CPU.cmp.hdb
RISC CPU/db/CPU.cmp.kpt
RISC CPU/db/CPU.cmp.logdb
RISC CPU/db/CPU.cmp.rdb
RISC CPU/db/CPU.cmp.tdb
RISC CPU/db/CPU.cmp0.ddb
RISC CPU/db/CPU.cmp2.ddb
RISC CPU/db/CPU.cmp_merge.kpt
RISC CPU/db/CPU.db_info
RISC CPU/db/CPU.eco.cdb
RISC CPU/db/CPU.fit.qmsg
RISC CPU/db/CPU.hier_info
RISC CPU/db/CPU.hif
RISC CPU/db/CPU.lpc.html
RISC CPU/db/CPU.lpc.rdb
RISC CPU/db/CPU.lpc.txt
RISC CPU/db/CPU.map.bpm
RISC CPU/db/CPU.map.cdb
RISC CPU/db/CPU.map.ecobp
RISC CPU/db/CPU.map.hdb
RISC CPU/db/CPU.map.kpt
RISC CPU/db/CPU.map.logdb
RISC CPU/db/CPU.map.qmsg
RISC CPU/db/CPU.map_bb.cdb
RISC CPU/db/CPU.map_bb.hdb
RISC CPU/db/CPU.map_bb.logdb
RISC CPU/db/CPU.pre_map.cdb
RISC CPU/db/CPU.pre_map.hdb
RISC CPU/db/CPU.rpp.qmsg
RISC CPU/db/CPU.rtlv.hdb
RISC CPU/db/CPU.rtlv_sg.cdb
RISC CPU/db/CPU.rtlv_sg_swap.cdb
RISC CPU/db/CPU.sgate.rvd
RISC CPU/db/CPU.sgate_sm.rvd
RISC CPU/db/CPU.sgdiff.cdb
RISC CPU/db/CPU.sgdiff.hdb
RISC CPU/db/CPU.sld_design_entry.sci
RISC CPU/db/CPU.sld_design_entry_dsc.sci
RISC CPU/db/CPU.syn_hier_info
RISC CPU/db/CPU.tan.qmsg
RISC CPU/db/CPU.tis_db_list.ddb
RISC CPU/db/CPU.tmw_info
RISC CPU/db/CPU_global_asgn_op.abo
RISC CPU/db/decode_1oa.tdf
RISC CPU/db/mux_hib.tdf
RISC CPU/db/prev_cmp_CPU.asm.qmsg
RISC CPU/db/prev_cmp_CPU.fit.qmsg
RISC CPU/db/prev_cmp_CPU.map.qmsg
RISC CPU/db/prev_cmp_CPU.qmsg
RISC CPU/db/prev_cmp_CPU.tan.qmsg
RISC CPU/db/wed.wsf
RISC CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.atm
RISC CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.dfp
RISC CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.hdbx
RISC CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.kpt
RISC CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.logdb
RISC CPU/incremental_db/compiled_partitions/CPU.root_partition.cmp.rcf
RISC CPU/incremental_db/compiled_partitions/CPU.root_partition.map.atm
RISC CPU/incremental_db/compiled_partitions/CPU.root_partition.map.dpi
RISC CPU/incremental_db/compiled_partitions/CPU.root_partition.map.hdbx
RISC CPU/incremental_db/compiled_partitions/CPU.root_partition.map.kpt
RISC CPU/incremental_db/README
RISC CPU/machine.v
RISC CPU/machine.v.bak
RISC CPU/modelsim.ini
RISC CPU/register.v
RISC CPU/register.v.bak
RISC CPU/risc_cpu.v
RISC CPU/rom.v.bak
RISC CPU/transcript
RISC CPU/vsim.wlf
RISC CPU/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.asm
RISC CPU/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/verilog.rw
RISC CPU/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dat
RISC CPU/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.dbs
RISC CPU/work/@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s/_primary.vhd
RISC CPU/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dat
RISC CPU/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.dbs
RISC CPU/work/@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n/_primary.vhd
RISC CPU/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.asm
RISC CPU/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/verilog.rw
RISC CPU/work/@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n/_primary.dat
RISC CPU/work/@a@l

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