文件名称:rel_08_done
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- 上传时间：2012-11-12
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文件大小：247.12kb
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修改自OpenCores的黑白棋游戏代码。采用VGA输出显示，PS2键盘（W、A、S、D、回车）输入控制，实现AI，LED灯指示是否游戏结束，VGA显示频率25MHz，系统频率50MHz，经过Cyclone IV芯片EP4CE115F29C7N的板级调试，实现全部功能，文件夹下有rtl源代码，管脚定义pin文件，和可以直接进行JTAG烧写和E2PROM烧写的pof和sof文件，-Modified from OpenCores Othello game code. Using the VGA output display, PS2 keyboard (W, A, S, D, Enter) input control to achieve AI, LED lights indicate whether the game is over, VGA display frequency of 25MHz, the system frequency of 50MHz, after Cyclone IV chip, board-level debugging EP4CE115F29C7N to achieve full functionality, folder there rtl source code, pin definition of pin file, and can be programmed and the JTAG programming of pof and E2PROM sof file,
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下载文件列表
rel_08_done/readme.txt
rel_08_done/reversi.pin
rel_08_done/reversi.pof
rel_08_done/reversi.sof
rel_08_done/rtl/board_move.v
rel_08_done/rtl/b_move.v
rel_08_done/rtl/game_ai.v
rel_08_done/rtl/greybox_tmp/cbx_args.txt
rel_08_done/rtl/heuristics.v
rel_08_done/rtl/hvsync_gen.v
rel_08_done/rtl/memory_bram.v
rel_08_done/rtl/moves_map.v
rel_08_done/rtl/move_cell.v
rel_08_done/rtl/negedge_detect.v
rel_08_done/rtl/negedge_detect.v.bak
rel_08_done/rtl/pll.qip
rel_08_done/rtl/pll.v
rel_08_done/rtl/pll_bb.v
rel_08_done/rtl/ps2_decoder.v
rel_08_done/rtl/ps2_decoder.v.bak
rel_08_done/rtl/ps2_top.v
rel_08_done/rtl/ps2_top.v.bak
rel_08_done/rtl/RB_cnt.v
rel_08_done/rtl/reversi.v
rel_08_done/rtl/reversi.v.bak
rel_08_done/rtl/rs232.v
rel_08_done/rtl/time_analysis.v
rel_08_done/rtl/vga_controller.v
rel_08_done/rtl/vga_controller.v.bak
rel_08_done/rtl/xy_calculate.v
rel_08_done/rtl/xy_calculate.v.bak
rel_08_done/rtl/greybox_tmp
rel_08_done/rtl
rel_08_done
rel_08_done/reversi.pin
rel_08_done/reversi.pof
rel_08_done/reversi.sof
rel_08_done/rtl/board_move.v
rel_08_done/rtl/b_move.v
rel_08_done/rtl/game_ai.v
rel_08_done/rtl/greybox_tmp/cbx_args.txt
rel_08_done/rtl/heuristics.v
rel_08_done/rtl/hvsync_gen.v
rel_08_done/rtl/memory_bram.v
rel_08_done/rtl/moves_map.v
rel_08_done/rtl/move_cell.v
rel_08_done/rtl/negedge_detect.v
rel_08_done/rtl/negedge_detect.v.bak
rel_08_done/rtl/pll.qip
rel_08_done/rtl/pll.v
rel_08_done/rtl/pll_bb.v
rel_08_done/rtl/ps2_decoder.v
rel_08_done/rtl/ps2_decoder.v.bak
rel_08_done/rtl/ps2_top.v
rel_08_done/rtl/ps2_top.v.bak
rel_08_done/rtl/RB_cnt.v
rel_08_done/rtl/reversi.v
rel_08_done/rtl/reversi.v.bak
rel_08_done/rtl/rs232.v
rel_08_done/rtl/time_analysis.v
rel_08_done/rtl/vga_controller.v
rel_08_done/rtl/vga_controller.v.bak
rel_08_done/rtl/xy_calculate.v
rel_08_done/rtl/xy_calculate.v.bak
rel_08_done/rtl/greybox_tmp
rel_08_done/rtl
rel_08_done
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