文件名称:IPcore
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所属分类:
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- 上传时间:2012-11-13
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文件大小:5.2mb
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已下载:0次
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相关连接:无下载说明:别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容来自于网络,使用问题请自行百度
FPGA 的各种 ip core 供大家参考-FPGA various ip core for your reference
(系统自动生成,下载前可以参看下载内容)
下载文件列表
IP核/395_vgs.tar.gz
IP核/3des_vhdl.tar.gz
IP核/51/8051软核使用步骤.pdf
IP核/51/CPU_Core.vqm
IP核/ata.tar.gz
IP核/AVR_Core.tar.gz
IP核/camera.tar.gz
IP核/core_arm.tar.gz
IP核/i2c/bench/CVS/Entries
IP核/i2c/bench/CVS/Repository
IP核/i2c/bench/CVS/Root
IP核/i2c/bench/verilog/CVS/Entries
IP核/i2c/bench/verilog/CVS/Repository
IP核/i2c/bench/verilog/CVS/Root
IP核/i2c/bench/verilog/i2c_slave_model.v
IP核/i2c/bench/verilog/spi_slave_model.v
IP核/i2c/bench/verilog/tst_bench_top.v
IP核/i2c/bench/verilog/wb_master_model.v
IP核/i2c/CVS/Entries
IP核/i2c/CVS/Repository
IP核/i2c/CVS/Root
IP核/i2c/doc/CVS/Entries
IP核/i2c/doc/CVS/Repository
IP核/i2c/doc/CVS/Root
IP核/i2c/doc/i2c_specs.pdf
IP核/i2c/doc/src/CVS/Entries
IP核/i2c/doc/src/CVS/Repository
IP核/i2c/doc/src/CVS/Root
IP核/i2c/doc/src/I2C_specs.doc
IP核/i2c/documentation/CVS/Entries
IP核/i2c/documentation/CVS/Repository
IP核/i2c/documentation/CVS/Root
IP核/i2c/rtl/CVS/Entries
IP核/i2c/rtl/CVS/Repository
IP核/i2c/rtl/CVS/Root
IP核/i2c/rtl/verilog/CVS/Entries
IP核/i2c/rtl/verilog/CVS/Repository
IP核/i2c/rtl/verilog/CVS/Root
IP核/i2c/rtl/verilog/i2c_master_bit_ctrl.v
IP核/i2c/rtl/verilog/i2c_master_byte_ctrl.v
IP核/i2c/rtl/verilog/i2c_master_defines.v
IP核/i2c/rtl/verilog/i2c_master_top.v
IP核/i2c/rtl/verilog/timescale.v
IP核/i2c/rtl/vhdl/CVS/Entries
IP核/i2c/rtl/vhdl/CVS/Repository
IP核/i2c/rtl/vhdl/CVS/Root
IP核/i2c/rtl/vhdl/I2C.VHD
IP核/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
IP核/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
IP核/i2c/rtl/vhdl/i2c_master_top.vhd
IP核/i2c/rtl/vhdl/readme
IP核/i2c/rtl/vhdl/tst_ds1621.vhd
IP核/i2c/sim/CVS/Entries
IP核/i2c/sim/CVS/Repository
IP核/i2c/sim/CVS/Root
IP核/i2c/sim/i2c_verilog/CVS/Entries
IP核/i2c/sim/i2c_verilog/CVS/Repository
IP核/i2c/sim/i2c_verilog/CVS/Root
IP核/i2c/sim/i2c_verilog/run/bench.vcd
IP核/i2c/sim/i2c_verilog/run/CVS/Entries
IP核/i2c/sim/i2c_verilog/run/CVS/Repository
IP核/i2c/sim/i2c_verilog/run/CVS/Root
IP核/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
IP核/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
IP核/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
IP核/i2c/sim/i2c_verilog/run/ncverilog.key
IP核/i2c/sim/i2c_verilog/run/ncverilog.log
IP核/i2c/sim/i2c_verilog/run/run
IP核/i2c/sim/i2c_verilog/run/waves/CVS/Entries
IP核/i2c/sim/i2c_verilog/run/waves/CVS/Repository
IP核/i2c/sim/i2c_verilog/run/waves/CVS/Root
IP核/i2c/software/CVS/Entries
IP核/i2c/software/CVS/Repository
IP核/i2c/software/CVS/Root
IP核/i2c/software/drivers/CVS/Entries
IP核/i2c/software/drivers/CVS/Repository
IP核/i2c/software/drivers/CVS/Root
IP核/i2c/software/include/CVS/Entries
IP核/i2c/software/include/CVS/Repository
IP核/i2c/software/include/CVS/Root
IP核/i2c/software/include/oc_i2c_master.h
IP核/i2c/verilog/CVS/Entries
IP核/i2c/verilog/CVS/Repository
IP核/i2c/verilog/CVS/Root
IP核/i2c/vhdl/CVS/Entries
IP核/i2c/vhdl/CVS/Repository
IP核/i2c/vhdl/CVS/Root
IP核/i2c.tar.gz
IP核/jtag.tar.gz
IP核/memory_cores.tar.gz
IP核/memory_cores2.tar.gz
IP核/memory_sizer.tar.gz
IP核/pci_core.tar.gz
IP核/sdram_ctrl.tar.gz
IP核/usb11.tar.gz
IP核/video_compression_systems.tar.gz
IP核/i2c/sim/i2c_verilog/run/INCA_libs/CVS
IP核/i2c/sim/i2c_verilog/run/waves/CVS
IP核/i2c/sim/i2c_verilog/run/CVS
IP核/i2c/sim/i2c_verilog/run/INCA_libs
IP核/i2c/sim/i2c_verilog/run/waves
IP核/i2c/bench/verilog/CVS
IP核/i2c/doc/src/CVS
IP核/i2c/rtl/verilog/CVS
IP核/i2c/rtl/vhdl/CVS
IP核/i2c/sim/i2c_verilog/CVS
IP核/i2c/sim/i2c_verilog/run
IP核/i2c/software/drivers/CVS
IP核/i2c/software/include/CVS
IP核/i2c/bench/CVS
IP核/i2c/bench/verilog
IP核/i2c/doc/CVS
IP核/i2c/doc/src
IP核/i2c/documentation/CVS
IP核/i2c/rtl/CVS
IP核/i2c/rtl/verilog
IP核/i2c/rtl/vhdl
IP核/i2c/sim/CVS
IP核/i2c/sim/i2c_verilog
IP核/i2c/software/CVS
IP核/i2c/software/drivers
IP核/i2c/software/include
IP核/i2c/verilog/CVS
IP核/i2c/vhdl/CVS
IP核/i2c/bench
IP核/i2c/CVS
IP核/i2c/doc
IP核/i2c/documentation
IP核/i2c/rtl
IP核/i2c/sim
IP核/i2c/software
IP核/i2c/verilog
IP核/i2c/vhdl
IP核/51
IP核/i2c
IP核
IP核/3des_vhdl.tar.gz
IP核/51/8051软核使用步骤.pdf
IP核/51/CPU_Core.vqm
IP核/ata.tar.gz
IP核/AVR_Core.tar.gz
IP核/camera.tar.gz
IP核/core_arm.tar.gz
IP核/i2c/bench/CVS/Entries
IP核/i2c/bench/CVS/Repository
IP核/i2c/bench/CVS/Root
IP核/i2c/bench/verilog/CVS/Entries
IP核/i2c/bench/verilog/CVS/Repository
IP核/i2c/bench/verilog/CVS/Root
IP核/i2c/bench/verilog/i2c_slave_model.v
IP核/i2c/bench/verilog/spi_slave_model.v
IP核/i2c/bench/verilog/tst_bench_top.v
IP核/i2c/bench/verilog/wb_master_model.v
IP核/i2c/CVS/Entries
IP核/i2c/CVS/Repository
IP核/i2c/CVS/Root
IP核/i2c/doc/CVS/Entries
IP核/i2c/doc/CVS/Repository
IP核/i2c/doc/CVS/Root
IP核/i2c/doc/i2c_specs.pdf
IP核/i2c/doc/src/CVS/Entries
IP核/i2c/doc/src/CVS/Repository
IP核/i2c/doc/src/CVS/Root
IP核/i2c/doc/src/I2C_specs.doc
IP核/i2c/documentation/CVS/Entries
IP核/i2c/documentation/CVS/Repository
IP核/i2c/documentation/CVS/Root
IP核/i2c/rtl/CVS/Entries
IP核/i2c/rtl/CVS/Repository
IP核/i2c/rtl/CVS/Root
IP核/i2c/rtl/verilog/CVS/Entries
IP核/i2c/rtl/verilog/CVS/Repository
IP核/i2c/rtl/verilog/CVS/Root
IP核/i2c/rtl/verilog/i2c_master_bit_ctrl.v
IP核/i2c/rtl/verilog/i2c_master_byte_ctrl.v
IP核/i2c/rtl/verilog/i2c_master_defines.v
IP核/i2c/rtl/verilog/i2c_master_top.v
IP核/i2c/rtl/verilog/timescale.v
IP核/i2c/rtl/vhdl/CVS/Entries
IP核/i2c/rtl/vhdl/CVS/Repository
IP核/i2c/rtl/vhdl/CVS/Root
IP核/i2c/rtl/vhdl/I2C.VHD
IP核/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
IP核/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
IP核/i2c/rtl/vhdl/i2c_master_top.vhd
IP核/i2c/rtl/vhdl/readme
IP核/i2c/rtl/vhdl/tst_ds1621.vhd
IP核/i2c/sim/CVS/Entries
IP核/i2c/sim/CVS/Repository
IP核/i2c/sim/CVS/Root
IP核/i2c/sim/i2c_verilog/CVS/Entries
IP核/i2c/sim/i2c_verilog/CVS/Repository
IP核/i2c/sim/i2c_verilog/CVS/Root
IP核/i2c/sim/i2c_verilog/run/bench.vcd
IP核/i2c/sim/i2c_verilog/run/CVS/Entries
IP核/i2c/sim/i2c_verilog/run/CVS/Repository
IP核/i2c/sim/i2c_verilog/run/CVS/Root
IP核/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
IP核/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
IP核/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
IP核/i2c/sim/i2c_verilog/run/ncverilog.key
IP核/i2c/sim/i2c_verilog/run/ncverilog.log
IP核/i2c/sim/i2c_verilog/run/run
IP核/i2c/sim/i2c_verilog/run/waves/CVS/Entries
IP核/i2c/sim/i2c_verilog/run/waves/CVS/Repository
IP核/i2c/sim/i2c_verilog/run/waves/CVS/Root
IP核/i2c/software/CVS/Entries
IP核/i2c/software/CVS/Repository
IP核/i2c/software/CVS/Root
IP核/i2c/software/drivers/CVS/Entries
IP核/i2c/software/drivers/CVS/Repository
IP核/i2c/software/drivers/CVS/Root
IP核/i2c/software/include/CVS/Entries
IP核/i2c/software/include/CVS/Repository
IP核/i2c/software/include/CVS/Root
IP核/i2c/software/include/oc_i2c_master.h
IP核/i2c/verilog/CVS/Entries
IP核/i2c/verilog/CVS/Repository
IP核/i2c/verilog/CVS/Root
IP核/i2c/vhdl/CVS/Entries
IP核/i2c/vhdl/CVS/Repository
IP核/i2c/vhdl/CVS/Root
IP核/i2c.tar.gz
IP核/jtag.tar.gz
IP核/memory_cores.tar.gz
IP核/memory_cores2.tar.gz
IP核/memory_sizer.tar.gz
IP核/pci_core.tar.gz
IP核/sdram_ctrl.tar.gz
IP核/usb11.tar.gz
IP核/video_compression_systems.tar.gz
IP核/i2c/sim/i2c_verilog/run/INCA_libs/CVS
IP核/i2c/sim/i2c_verilog/run/waves/CVS
IP核/i2c/sim/i2c_verilog/run/CVS
IP核/i2c/sim/i2c_verilog/run/INCA_libs
IP核/i2c/sim/i2c_verilog/run/waves
IP核/i2c/bench/verilog/CVS
IP核/i2c/doc/src/CVS
IP核/i2c/rtl/verilog/CVS
IP核/i2c/rtl/vhdl/CVS
IP核/i2c/sim/i2c_verilog/CVS
IP核/i2c/sim/i2c_verilog/run
IP核/i2c/software/drivers/CVS
IP核/i2c/software/include/CVS
IP核/i2c/bench/CVS
IP核/i2c/bench/verilog
IP核/i2c/doc/CVS
IP核/i2c/doc/src
IP核/i2c/documentation/CVS
IP核/i2c/rtl/CVS
IP核/i2c/rtl/verilog
IP核/i2c/rtl/vhdl
IP核/i2c/sim/CVS
IP核/i2c/sim/i2c_verilog
IP核/i2c/software/CVS
IP核/i2c/software/drivers
IP核/i2c/software/include
IP核/i2c/verilog/CVS
IP核/i2c/vhdl/CVS
IP核/i2c/bench
IP核/i2c/CVS
IP核/i2c/doc
IP核/i2c/documentation
IP核/i2c/rtl
IP核/i2c/sim
IP核/i2c/software
IP核/i2c/verilog
IP核/i2c/vhdl
IP核/51
IP核/i2c
IP核
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