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文件名称:Lab_ISE_Led

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  • 上传时间:
    2008-10-13
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    761.56kb
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介绍说明--下载内容来自于网络,使用问题请自行百度

vhdl实例教程,其中的例子适合新手演示使用,肯定会有帮助的。-VHDL example tutorial, an example of the use for novice demo, it will certainly help.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/automake.log
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/bitgen.ut
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.bgn
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.bit
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.drc
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.cmd_log
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/_impact.log
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/_impact.cmd
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.lso
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.mcs
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/simple_led.ise
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/simple_led.dhp
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.ngm
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.pad_txt
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.pcf
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.prj
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.prm
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.sig
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.stx
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.syr
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.ucf
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.ucf.untf
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.ut
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.v
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg_cclktemp.bit
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/__projnav.log
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/xst/work/hdllib.ref
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/xst/work/vlg6F/seven_seg.bin
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/xst/work/vlg6F/seven__seg.bin
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/xst/work/vlg6F
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/xst/work
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/xst/dump.xst/seven_seg.prj/ngx/opt
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/xst/dump.xst/seven_seg.prj/ngx/notopt
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/xst/dump.xst/seven_seg.prj/ngx
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/xst/dump.xst/seven_seg.prj
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/xst/dump.xst
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/xst
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/_ngo/netlist.lst
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/_ngo
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/__projnav/bitgen.rsp
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/__projnav/ednTOngd_tcl.rsp
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/__projnav/nc1TOncd_tcl.rsp
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/__projnav/runXst_tcl.rsp
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/__projnav/seven_seg.xst
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/__projnav/seven_seg_ncdTOut_tcl.rsp
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/__projnav/simple_led.gfl
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/__projnav/simple_led_flowplus.gfl
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/__projnav/sumrpt_tcl.rsp
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/__projnav
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/simple_led_ise6_bak.zip
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg_summary.html
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/_xmsgs
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg_vhdl.prj
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.ngr
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.ngc
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/simple_led.ise_ISE_Backup
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.bld
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.ngd
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg_map.ngm
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg_map.ncd
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.nc1
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.mrp
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg_last_par.ncd
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.par
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg_pad.csv
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.pad
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg_pad.txt
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.ncd
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.xpi
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.placed_ncd_tracker
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.routed_ncd_tracker
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.twx
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63/seven_seg.twr
Lab_ISE_Led/3SLC_SimpleLED_Verilog_ISE63
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/automake.log
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/bitgen.ut
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/clkdll_divide.vhd
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/coregen.log
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/coregen.prj
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/my_testbench.tdo
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/readme.txt
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/seven_seg.bld
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/seven_seg.cmd_log
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/seven_seg.lso
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/seven_seg.mcs
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/seven_seg.mrp
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/seven_seg.nc1
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/seven_seg.ngc
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/seven_seg.ngd
Lab_ISE_Led/3SLC_LED_VHDL_ISE63/seven_seg.ngm
Lab_ISE_Led/3SLC_LED_VHDL_IS

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