原理图常见错误： （1）ERC报告管脚没有接入信号： a. 创建封装时给管脚定义了I/O属性； b.创建元件或放置元件时修改了不一致的grid属性，管脚与线没有连上； c. 创建元件时pin方向反向，必须非pin name端连线。 （2）元件跑到图纸界外：没有在元件库图表纸中心创建元件。 （3）创建的工程文件网络表只能部分调入pcb：生成netlist时没有选择为global。 （4）当使用自己创建的多部分组成的元件时，千万不要使用annotate.-principle of common mistakes : (1) ERC report no access to signal pins : a. creation package to the pin at the definition of I / O attribute; b. create components or modify components placed inconsistent grid attributes, and the lines do not pin connection; c. create components reverse direction when the pin, non-name-pin connections. (2) components went to the drawings profession : no paper charts component library center components. (3) the creation of the document network table works only partially transferred PCB : netlist generation did not choose to global. (4) When the use of their own creation, multi-component element, we must use annotate.