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文件名称:OpenRISC

  • 所属分类：
    VHDL-FPGA-Verilog
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    2.47mb
  • 已下载：
    0次
  • 提 供 者：
    1***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

一个开放的risc，已应用到实际中，可以借鉴的不少，大家-an open RISC, has been applied to practice, we can draw a lot, we look at
相关搜索： openrisc RISC or1200_cpu.v open risc OR1200 OpenRI or1200_dc_top synopsys or1200_spec.d

(系统自动生成,下载前可以参看下载内容)

下载文件列表

OpenRISC/or1200_overview.pdf
OpenRISC/or1200_spec.doc
OpenRISC/or1200_spec.pdf
OpenRISC/or1k_or1200.tar.gz
OpenRISC/or1k_or1200/or1k_or1200.tar.tar
OpenRISC/or1k_or1200/or1k/or1200/bench/README
OpenRISC/or1k_or1200/or1k/or1200/bench
OpenRISC/or1k_or1200/or1k/or1200/doc/or1200_spec.doc
OpenRISC/or1k_or1200/or1k/or1200/doc/or1200_spec.pdf
OpenRISC/or1k_or1200/or1k/or1200/doc
OpenRISC/or1k_or1200/or1k/or1200/lib/README
OpenRISC/or1k_or1200/or1k/or1200/lib
OpenRISC/or1k_or1200/or1k/or1200/lint/bin/README
OpenRISC/or1k_or1200/or1k/or1200/lint/bin/run_lint
OpenRISC/or1k_or1200/or1k/or1200/lint/bin
OpenRISC/or1k_or1200/or1k/or1200/lint/log/README
OpenRISC/or1k_or1200/or1k/or1200/lint/log
OpenRISC/or1k_or1200/or1k/or1200/lint/run/README
OpenRISC/or1k_or1200/or1k/or1200/lint/run
OpenRISC/or1k_or1200/or1k/or1200/lint
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_alu.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_amultp2_32x32.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_cfgr.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_cpu.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_ctrl.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_dc_fsm.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_dc_ram.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_dc_tag.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_dc_top.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_defines.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_dmmu_tlb.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_dmmu_top.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_dpram_32x32.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_du.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_except.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_freeze.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_genpc.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_gmultp2_32x32.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_ic_fsm.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_ic_ram.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_ic_tag.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_ic_top.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_if.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_immu_tlb.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_immu_top.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_iwb_biu.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_lsu.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_mem2reg.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_mult_mac.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_operandmuxes.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_pic.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_pm.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_qmem_top.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_reg2mem.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_rf.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_rfram_generic.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_sb.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_sb_fifo.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_spram_1024x32.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_spram_1024x8.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_spram_2048x32.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_spram_2048x8.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_spram_256x21.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_spram_512x20.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_spram_64x14.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_spram_64x22.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_spram_64x24.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_sprs.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_top.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_tpram_32x32.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_tt.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_wb_biu.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_wbmux.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
OpenRISC/or1k_or1200/or1k/or1200/rtl/verilog
OpenRISC/or1k_or1200/or1k/or1200/rtl
OpenRISC/or1k_or1200/or1k/or1200/sim/README
OpenRISC/or1k_or1200/or1k/or1200/sim
OpenRISC/or1k_or1200/or1k/or1200/syn/gate
OpenRISC/or1k_or1200/or1k/or1200/syn/log
OpenRISC/or1k_or1200/or1k/or1200/syn/scr
OpenRISC/or1k_or1200/or1k/or1200/syn/synopsys/bin/README
OpenRISC/or1k_or1200/or1k/or1200/syn/synopsys/bin/read_design.inc
OpenRISC/or1k_or1200/or1k/or1200/syn/synopsys/bin/run_syn
OpenRISC/or1k_or1200/or1k/or1200/syn/synopsys/bin/top.scr
OpenRISC/or1k_or1200/or1k/or1200/syn/synopsys/bin
OpenRISC/or1k_or1200/or1k/or1200/syn/synopsys/log/README
OpenRISC/or1k_or1200/or1k/or1200/syn/synopsys/log
OpenRISC/or1k_or1200/or1k/or1200/syn/synopsys/out/README
OpenRISC/or1k_or1200/or1k/or1200/syn/synopsys/out
OpenRISC/

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