文件名称:sdram_all
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- 上传时间:2012-11-16
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文件大小:493.79kb
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sdram 控制器的verilog 实现,包括用户逻辑和控制器的设计-SDRAM controller Verilog realization, including user logic and controller design
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下载文件列表
sdram_all/db
sdram_all/delay_reset/counter.bsf
sdram_all/delay_reset/counter.v
sdram_all/delay_reset/reset.bdf
sdram_all/delay_reset/reset.bsf
sdram_all/delay_reset
sdram_all/pic/init1.jpg
sdram_all/pic/init2.jpg
sdram_all/pic/read_burst.jpg
sdram_all/pic/refresh_req_ack.jpg
sdram_all/pic/Thumbs.db
sdram_all/pic/write_burst.jpg
sdram_all/pic
sdram_all/pll/pll_50.bsf
sdram_all/pll/pll_50.cmp
sdram_all/pll/pll_50.inc
sdram_all/pll/pll_50.ppf
sdram_all/pll/pll_50.v
sdram_all/pll/pll_50_bb.v
sdram_all/pll/pll_50_inst.v
sdram_all/pll/pll_50_wave0.jpg
sdram_all/pll/pll_50_waveforms.html
sdram_all/pll
sdram_all/source_sdram/init_fsm.v
sdram_all/source_sdram/main_fsm.v
sdram_all/source_sdram/refresh.v
sdram_all/source_sdram/sdram_top.bsf
sdram_all/source_sdram/sdram_top.v
sdram_all/source_sdram/sdr_par.v
sdram_all/source_sdram/sdr_sig.v
sdram_all/source_sdram
sdram_all/source_user/ram512.bsf
sdram_all/source_user/ram512.hex
sdram_all/source_user/ram512.mif
sdram_all/source_user/ram512.v
sdram_all/source_user/rom256.bsf
sdram_all/source_user/rom256.v
sdram_all/source_user/rom_value.hex
sdram_all/source_user/rom_value.mif
sdram_all/source_user/user_interface.bsf
sdram_all/source_user/user_interface.v
sdram_all/source_user/user_interface.v.bak
sdram_all/source_user
sdram_all/testbench/singal.do
sdram_all/testbench/singal.do.bak
sdram_all/testbench/testbench.v
sdram_all/testbench/testbench.v.bak
sdram_all/testbench
sdram_all/top.asm.rpt
sdram_all/top.bdf
sdram_all/top.done
sdram_all/top.dpf
sdram_all/top.eda.rpt
sdram_all/top.fit.rpt
sdram_all/top.fit.smsg
sdram_all/top.fit.summary
sdram_all/top.flow.rpt
sdram_all/top.jdi
sdram_all/top.map.rpt
sdram_all/top.map.summary
sdram_all/top.pin
sdram_all/top.pof
sdram_all/top.qpf
sdram_all/top.qsf
sdram_all/top.qws
sdram_all/top.sof
sdram_all/top.stp
sdram_all/top.tan.rpt
sdram_all/top.tan.summary
sdram_all/top.v
sdram_all/top_nativelink_simulation.rpt
sdram_all
sdram_all/delay_reset/counter.bsf
sdram_all/delay_reset/counter.v
sdram_all/delay_reset/reset.bdf
sdram_all/delay_reset/reset.bsf
sdram_all/delay_reset
sdram_all/pic/init1.jpg
sdram_all/pic/init2.jpg
sdram_all/pic/read_burst.jpg
sdram_all/pic/refresh_req_ack.jpg
sdram_all/pic/Thumbs.db
sdram_all/pic/write_burst.jpg
sdram_all/pic
sdram_all/pll/pll_50.bsf
sdram_all/pll/pll_50.cmp
sdram_all/pll/pll_50.inc
sdram_all/pll/pll_50.ppf
sdram_all/pll/pll_50.v
sdram_all/pll/pll_50_bb.v
sdram_all/pll/pll_50_inst.v
sdram_all/pll/pll_50_wave0.jpg
sdram_all/pll/pll_50_waveforms.html
sdram_all/pll
sdram_all/source_sdram/init_fsm.v
sdram_all/source_sdram/main_fsm.v
sdram_all/source_sdram/refresh.v
sdram_all/source_sdram/sdram_top.bsf
sdram_all/source_sdram/sdram_top.v
sdram_all/source_sdram/sdr_par.v
sdram_all/source_sdram/sdr_sig.v
sdram_all/source_sdram
sdram_all/source_user/ram512.bsf
sdram_all/source_user/ram512.hex
sdram_all/source_user/ram512.mif
sdram_all/source_user/ram512.v
sdram_all/source_user/rom256.bsf
sdram_all/source_user/rom256.v
sdram_all/source_user/rom_value.hex
sdram_all/source_user/rom_value.mif
sdram_all/source_user/user_interface.bsf
sdram_all/source_user/user_interface.v
sdram_all/source_user/user_interface.v.bak
sdram_all/source_user
sdram_all/testbench/singal.do
sdram_all/testbench/singal.do.bak
sdram_all/testbench/testbench.v
sdram_all/testbench/testbench.v.bak
sdram_all/testbench
sdram_all/top.asm.rpt
sdram_all/top.bdf
sdram_all/top.done
sdram_all/top.dpf
sdram_all/top.eda.rpt
sdram_all/top.fit.rpt
sdram_all/top.fit.smsg
sdram_all/top.fit.summary
sdram_all/top.flow.rpt
sdram_all/top.jdi
sdram_all/top.map.rpt
sdram_all/top.map.summary
sdram_all/top.pin
sdram_all/top.pof
sdram_all/top.qpf
sdram_all/top.qsf
sdram_all/top.qws
sdram_all/top.sof
sdram_all/top.stp
sdram_all/top.tan.rpt
sdram_all/top.tan.summary
sdram_all/top.v
sdram_all/top_nativelink_simulation.rpt
sdram_all
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