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文件名称:DDR_32Mx16_SimulationModel

  • 所属分类：
    Windows Develop
  • 标签属性：
    [ASM] [源码]
  • 上传时间：
    2012-11-16
  • 文件大小：
    1.79mb
  • 已下载：
    0次
  • 提 供 者：
    sh***
  • 相关连接：
    无
  • 下载说明：
    别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容来自于网络，使用问题请自行百度

sdram的仿真模型，包括的多个不同的模型，用于仿真-SDRAM simulation model, including a number of different models for the simulation
相关搜索： DDR_32Mx16_SimulationModel.zip DDR_32Mx16_SimulationModel

(系统自动生成,下载前可以参看下载内容)

下载文件列表

DDR_32Mx16_IBIS.zip
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/512MDDR.model
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/512MDDR.skew
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/512MDDR_CA.net
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/512MDDR_CA.sp
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/512MDDR_CLK.net
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/512MDDR_CLK.sp
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/512MDDR_DM.net
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/512MDDR_DM.sp
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/512MDDR_DQ.net
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/512MDDR_DQ.sp
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/66tsop.lib
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/HY5DU121622BTP_Spice_Model.pdf
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/HY5DU121622BTP_Spice_Model.ppt
DDR_32MX16_SPICE/DDR_GC_32MX16_HY5DU121622BTP_SPICE/mode_control.lib
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/512DDR_ca.sp
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/512DDR_clk.sp
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/512DDR_dm.sp
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/512DDR_dq.sp
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/66tsop.lib
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/HY5DU121622ATP_Spice_Model_Aug2004.pdf
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/HY5DU121622ATP_Spice_Model_Aug2004.ppt
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/max.inc
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/min.inc
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/mode_control.lib
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/SCH_CA.inc
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/SCH_CLK.inc
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/SCH_DM.inc
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/SCH_DQ.inc
DDR_32MX16_SPICE/DDR_PC_32MX16_HY5DU121622AT_SPICE/typ.inc
DDR_32Mx16_Verilog/DDR_1st_32Mx16_HY5DU121622T_VERILOG/DDR_1st_hy5du121622t.vp.vcs
DDR_32Mx16_Verilog/DDR_1st_32Mx16_HY5DU121622T_VERILOG/DDR_1st_hy5du121622t.vp.xl
DDR_32Mx16_Verilog/DDR_PC_32Mx16_HY5DU121622AT_VERILOG/DDR_PC_32Mx16_HY5DU121622AT.vcs
DDR_32Mx16_Verilog/DDR_PC_32Mx16_HY5DU121622AT_VERILOG/DDR_PC_32Mx16_HY5DU121622AT.xl
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_ModelSim/work/hy5du121622at/behavioral_model_hy5du121622at.asm
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_ModelSim/work/hy5du121622at/behavioral_model_hy5du121622at.dat
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_ModelSim/work/hy5du121622at/_primary.dat
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_ModelSim/work/hy5du121622at_pack/body.asm
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_ModelSim/work/hy5du121622at_pack/body.dat
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_ModelSim/work/hy5du121622at_pack/_primary.dat
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_ModelSim/work/hy5du121622at_pack/_vhdl.asm
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_ModelSim/work/_info
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_VSS/README
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_VSS/work/HY5DU121622AT.mra
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_VSS/work/HY5DU121622AT.sim
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_VSS/work/HY5DU121622AT_PACK.sim
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_VSS/work/HY5DU121622AT_PACK__.sim
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_VSS/work/HY5DU121622AT__BEHAVIORAL_MODEL_HY5DU121622AT.sim
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_VSS/work/sparcOS5/HY5DU121622AT.o
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_VSS/work/sparcOS5/HY5DU121622AT_PACK__.o
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)/DDR_PC_32Mx16_HY5DU121622A(L)T_VSS/work/sparcOS5/HY5DU121622AT__BEHAVIORAL_MODEL_HY5DU121622AT.o

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