文件名称:DDR_SDRAM_controller
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- 上传时间：2012-11-16
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文件大小：128.83kb
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DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
相关搜索： ddr
dcm
ddr sdram
ddr controller
sdram vhdl
ddr sdram controller vhdl code
vhdl code for ddr sdram controller
program to test ddr sdram controller vhdl
Virtex-4
ddr ii
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下载文件列表
DDR SDRAM控制器2/ddr_xilinx.pdf
DDR SDRAM控制器2/ddr_verilog_xilinx/define.v
DDR SDRAM控制器2/ddr_verilog_xilinx/glbl.v
DDR SDRAM控制器2/ddr_verilog_xilinx/mt46v4m16.v
DDR SDRAM控制器2/ddr_verilog_xilinx/readme.txt
DDR SDRAM控制器2/ddr_verilog_xilinx/string_decode_fn.v
DDR SDRAM控制器2/ddr_verilog_xilinx/tb_top.v
DDR SDRAM控制器2/ddr_verilog_xilinx/top.ucf
DDR SDRAM控制器2/ddr_verilog_xilinx/top_func.v
DDR SDRAM控制器2/ddr_verilog_xilinx
DDR SDRAM控制器2
DDR SDRAM控制器2/ddr_verilog_xilinx/define.v
DDR SDRAM控制器2/ddr_verilog_xilinx/glbl.v
DDR SDRAM控制器2/ddr_verilog_xilinx/mt46v4m16.v
DDR SDRAM控制器2/ddr_verilog_xilinx/readme.txt
DDR SDRAM控制器2/ddr_verilog_xilinx/string_decode_fn.v
DDR SDRAM控制器2/ddr_verilog_xilinx/tb_top.v
DDR SDRAM控制器2/ddr_verilog_xilinx/top.ucf
DDR SDRAM控制器2/ddr_verilog_xilinx/top_func.v
DDR SDRAM控制器2/ddr_verilog_xilinx
DDR SDRAM控制器2
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