文件名称:100vhdl_example
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vhdl语言的100个例子
VHDL语言100例
第1例 带控制端口的加法器
第2例 无控制端口的加法器
第3例 乘法器
第4例 比较器
第5例 二路选择器
第6例 寄存器
第7例 移位寄存器
第8例 综合单元库
第9例 七值逻辑与基本数据类型
第10例 函数
-VHDL language, VHDL language 100 examples of 100 cases of the first one cases of the control port with the first two cases of adder uncontrolled port adder section 3 cases of the first four cases of multiplier comparator section Selector Rd 5 cases of the first six cases of the first register 7 cases of the first eight cases of shift register integrated cell library the first nine cases of the seven-valued logic and basic data types the first 10 cases of function
VHDL语言100例
第1例 带控制端口的加法器
第2例 无控制端口的加法器
第3例 乘法器
第4例 比较器
第5例 二路选择器
第6例 寄存器
第7例 移位寄存器
第8例 综合单元库
第9例 七值逻辑与基本数据类型
第10例 函数
-VHDL language, VHDL language 100 examples of 100 cases of the first one cases of the control port with the first two cases of adder uncontrolled port adder section 3 cases of the first four cases of multiplier comparator section Selector Rd 5 cases of the first six cases of the first register 7 cases of the first eight cases of shift register integrated cell library the first nine cases of the seven-valued logic and basic data types the first 10 cases of function
相关搜索： 比较器
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下载文件列表
100vhdl_example/10_function/10_bit_to_int.vhd
100vhdl_example/10_function/README.TXT
100vhdl_example/11_wiredor/11_wiredor.vhd
100vhdl_example/11_wiredor/README.TXT
100vhdl_example/12_convert/12_convert.vhd
100vhdl_example/12_convert/README.TXT
100vhdl_example/13_SHL/13_SHL.VHD
100vhdl_example/13_SHL/README.TXT
100vhdl_example/14_MVL7_functions/14_MVL7_functions.vhd
100vhdl_example/14_MVL7_functions/README.TXT
100vhdl_example/15_MUX41/15_MUX41.VHD
100vhdl_example/15_MUX41/15_MVL7_functions.vhd
100vhdl_example/15_MUX41/15_MVL7_syn_types.vhd
100vhdl_example/15_MUX41/15_test_vectors_mux41.vhd
100vhdl_example/15_MUX41/15_TYPES.VHD
100vhdl_example/15_MUX41/README.TXT
100vhdl_example/16_MUX/16_multiple_mux.vhd
100vhdl_example/16_MUX/16_MVL7_functions.vhd
100vhdl_example/16_MUX/16_test_vectors.vhd
100vhdl_example/16_MUX/16_TYPES.VHD
100vhdl_example/16_MUX/README.TXT
100vhdl_example/16_MUX/TYPES.VHD
100vhdl_example/17_parity/17_parity.vhd
100vhdl_example/17_parity/17_test_bench.vhd
100vhdl_example/17_parity/README.TXT
100vhdl_example/18_LIB/18_tech_lib.vhd
100vhdl_example/18_LIB/18_test_lib.vhd
100vhdl_example/18_LIB/README.TXT
100vhdl_example/19_test_194/19_test_194.vhd
100vhdl_example/1_ADDER/1_ADDER/1_ADDER.exp
100vhdl_example/1_ADDER/1_ADDER/files/L1.rpt
100vhdl_example/1_ADDER/1_ADDER/files/L2.rpt
100vhdl_example/1_ADDER/1_ADDER/files/L3.rpt
100vhdl_example/1_ADDER/1_ADDER/workdirs/aa/ADDER.sim
100vhdl_example/1_ADDER/1_ADDER/workdirs/aa/ADDER.syn
100vhdl_example/1_ADDER/1_ADDER/workdirs/aa/Anal.info
100vhdl_example/1_ADDER/1_ADDER/workdirs/aa/Anal.out
100vhdl_example/1_ADDER/1_ADDER/workdirs/WORK/Anal.info
100vhdl_example/1_ADDER/1_ADDER/workdirs/WORK/Anal.out
100vhdl_example/1_ADDER/1_ADDER/workdirs/WORK/BIT_RTL_ADDER.sim
100vhdl_example/1_ADDER/1_ADDER/workdirs/WORK/BIT_RTL_ADDER.syn
100vhdl_example/1_ADDER/1_adder.acf
100vhdl_example/1_ADDER/1_adder.hif
100vhdl_example/1_ADDER/1_adder.mmf
100vhdl_example/1_ADDER/1_ADDER.VHD
100vhdl_example/1_ADDER/bir_rtl_adder.acf
100vhdl_example/1_ADDER/bir_rtl_adder.hif
100vhdl_example/1_ADDER/bir_rtl_adder.mmf
100vhdl_example/1_ADDER/bir_rtl_adder.tdf
100vhdl_example/1_ADDER/bit_rtl_adder.acf
100vhdl_example/1_ADDER/bit_rtl_adder.hif
100vhdl_example/1_ADDER/bit_rtl_adder.mmf
100vhdl_example/1_ADDER/bit_rtl_adder.vhd
100vhdl_example/1_ADDER/LIB.DLS
100vhdl_example/1_ADDER/README.TXT
100vhdl_example/1_ADDER/U2268397.DLS
100vhdl_example/20_test_159/20_test_159.vhd
100vhdl_example/21_test_13a/21_test_13a.vhd
100vhdl_example/22_deadlock/22_deadlock.vhd
100vhdl_example/23_test_120/23_Test_120.vhd
100vhdl_example/24_test_195/24_test_195.vhd
100vhdl_example/25_test_1/25_test_1.vhd
100vhdl_example/25_test_1/25_test_1a.vhd
100vhdl_example/26_test_74s/26_test_74s.vhd
100vhdl_example/27_test_16/27_test_16.vhd
100vhdl_example/28_test_64a/28_Test_64a.vhd
100vhdl_example/29_test_35/29_Test_35.vhd
100vhdl_example/2_ADDER/2_ADDER.VHD
100vhdl_example/2_ADDER/README.TXT
100vhdl_example/30_test_3/30_Test_3.vhd
100vhdl_example/31_test_35b/31_test_35b.vhd
100vhdl_example/32_test_110b/32_test_110b.vhd
100vhdl_example/33_comparer/33_COMP.VHD
100vhdl_example/33_comparer/33_comparer.vhd
100vhdl_example/33_comparer/33_SIMU.VHD
100vhdl_example/33_comparer/README.TXT
100vhdl_example/34_BUS/34_readwrite.VHD
100vhdl_example/34_BUS/34_readwrite_stim.vhd
100vhdl_example/34_BUS/README.TXT
100vhdl_example/35_486_bus/35_486_bus.vhd
100vhdl_example/35_486_bus/35_486_sys.vhd
100vhdl_example/35_486_bus/35_bit_pack.vhd
100vhdl_example/35_486_bus/35_bus_test.vhd
100vhdl_example/35_486_bus/35_ram_controller.vhd
100vhdl_example/35_486_bus/75_RAM.VHD
100vhdl_example/35_486_bus/README.TXT
100vhdl_example/36_GCD/36_GCD.VHD
100vhdl_example/36_GCD/36_TEST.VHD
100vhdl_example/36_GCD/README.TXT
100vhdl_example/37_test_105/37_test_105.vhd
100vhdl_example/38_test_28/38_Test_28.vhd
100vhdl_example/39_wst0dp/39_wst0dp.vhd
100vhdl_example/39_wst0dp/README.TXT
100vhdl_example/3_MUL/3_MUL.VHD
100vhdl_example/3_MUL/README.TXT
100vhdl_example/40_generic_dec/40_generic_dec.vhd
100vhdl_example/40_generic_dec/README.TXT
100vhdl_example/41_generic_testbench/40_generic_dec.vhd
100vhdl_example/41_generic_testbench/41_generic_testbench.vhd
100vhdl_example/41_generic_testbench/README.TXT
100vhdl_example/42_MIX/42_MIX.VHD
100vhdl_example/42_MIX/README.TXT
100vhdl_example/43_register/43_shift_reg.vhd
100vhdl_example/43_register/43_test_register.vhd
100vhdl_example/43_register/README.TXT
100vhdl_example/44_reg_counter/44_MVL7_functions.vhd
100vhdl_example/44_reg_counter/44_reg_counter.vhd
100vhdl_example/44_reg_counter/44_synthesis_types.vhd
100vhdl_example/44_reg_counter/44_test_vector.vhd
100vhdl_example/44_reg_counter/44_TYPES.VHD
100vhdl_example/44_reg_counter/README.TXT
100vhdl_example/45_test_63/45_test_63.vhd
100vhdl_example/46_generic/46_default_generic.vhd
100vhdl_example/46_generic/README.TXT
100vhdl_example/47_CONST/47_const_test.vhd
100vhdl_example/48_test_18e/48_test_18e.vhd
100vhdl_example/49_DELTA/49_TEST.VHD
100vhdl_example/4_COMP/4_COMP.VHD
100vhdl_example/4_COMP/README.TXT
100vhdl_example/50_test_18e/50_test_18e.vhd
100vhdl_example/51_te
100vhdl_example/10_function/README.TXT
100vhdl_example/11_wiredor/11_wiredor.vhd
100vhdl_example/11_wiredor/README.TXT
100vhdl_example/12_convert/12_convert.vhd
100vhdl_example/12_convert/README.TXT
100vhdl_example/13_SHL/13_SHL.VHD
100vhdl_example/13_SHL/README.TXT
100vhdl_example/14_MVL7_functions/14_MVL7_functions.vhd
100vhdl_example/14_MVL7_functions/README.TXT
100vhdl_example/15_MUX41/15_MUX41.VHD
100vhdl_example/15_MUX41/15_MVL7_functions.vhd
100vhdl_example/15_MUX41/15_MVL7_syn_types.vhd
100vhdl_example/15_MUX41/15_test_vectors_mux41.vhd
100vhdl_example/15_MUX41/15_TYPES.VHD
100vhdl_example/15_MUX41/README.TXT
100vhdl_example/16_MUX/16_multiple_mux.vhd
100vhdl_example/16_MUX/16_MVL7_functions.vhd
100vhdl_example/16_MUX/16_test_vectors.vhd
100vhdl_example/16_MUX/16_TYPES.VHD
100vhdl_example/16_MUX/README.TXT
100vhdl_example/16_MUX/TYPES.VHD
100vhdl_example/17_parity/17_parity.vhd
100vhdl_example/17_parity/17_test_bench.vhd
100vhdl_example/17_parity/README.TXT
100vhdl_example/18_LIB/18_tech_lib.vhd
100vhdl_example/18_LIB/18_test_lib.vhd
100vhdl_example/18_LIB/README.TXT
100vhdl_example/19_test_194/19_test_194.vhd
100vhdl_example/1_ADDER/1_ADDER/1_ADDER.exp
100vhdl_example/1_ADDER/1_ADDER/files/L1.rpt
100vhdl_example/1_ADDER/1_ADDER/files/L2.rpt
100vhdl_example/1_ADDER/1_ADDER/files/L3.rpt
100vhdl_example/1_ADDER/1_ADDER/workdirs/aa/ADDER.sim
100vhdl_example/1_ADDER/1_ADDER/workdirs/aa/ADDER.syn
100vhdl_example/1_ADDER/1_ADDER/workdirs/aa/Anal.info
100vhdl_example/1_ADDER/1_ADDER/workdirs/aa/Anal.out
100vhdl_example/1_ADDER/1_ADDER/workdirs/WORK/Anal.info
100vhdl_example/1_ADDER/1_ADDER/workdirs/WORK/Anal.out
100vhdl_example/1_ADDER/1_ADDER/workdirs/WORK/BIT_RTL_ADDER.sim
100vhdl_example/1_ADDER/1_ADDER/workdirs/WORK/BIT_RTL_ADDER.syn
100vhdl_example/1_ADDER/1_adder.acf
100vhdl_example/1_ADDER/1_adder.hif
100vhdl_example/1_ADDER/1_adder.mmf
100vhdl_example/1_ADDER/1_ADDER.VHD
100vhdl_example/1_ADDER/bir_rtl_adder.acf
100vhdl_example/1_ADDER/bir_rtl_adder.hif
100vhdl_example/1_ADDER/bir_rtl_adder.mmf
100vhdl_example/1_ADDER/bir_rtl_adder.tdf
100vhdl_example/1_ADDER/bit_rtl_adder.acf
100vhdl_example/1_ADDER/bit_rtl_adder.hif
100vhdl_example/1_ADDER/bit_rtl_adder.mmf
100vhdl_example/1_ADDER/bit_rtl_adder.vhd
100vhdl_example/1_ADDER/LIB.DLS
100vhdl_example/1_ADDER/README.TXT
100vhdl_example/1_ADDER/U2268397.DLS
100vhdl_example/20_test_159/20_test_159.vhd
100vhdl_example/21_test_13a/21_test_13a.vhd
100vhdl_example/22_deadlock/22_deadlock.vhd
100vhdl_example/23_test_120/23_Test_120.vhd
100vhdl_example/24_test_195/24_test_195.vhd
100vhdl_example/25_test_1/25_test_1.vhd
100vhdl_example/25_test_1/25_test_1a.vhd
100vhdl_example/26_test_74s/26_test_74s.vhd
100vhdl_example/27_test_16/27_test_16.vhd
100vhdl_example/28_test_64a/28_Test_64a.vhd
100vhdl_example/29_test_35/29_Test_35.vhd
100vhdl_example/2_ADDER/2_ADDER.VHD
100vhdl_example/2_ADDER/README.TXT
100vhdl_example/30_test_3/30_Test_3.vhd
100vhdl_example/31_test_35b/31_test_35b.vhd
100vhdl_example/32_test_110b/32_test_110b.vhd
100vhdl_example/33_comparer/33_COMP.VHD
100vhdl_example/33_comparer/33_comparer.vhd
100vhdl_example/33_comparer/33_SIMU.VHD
100vhdl_example/33_comparer/README.TXT
100vhdl_example/34_BUS/34_readwrite.VHD
100vhdl_example/34_BUS/34_readwrite_stim.vhd
100vhdl_example/34_BUS/README.TXT
100vhdl_example/35_486_bus/35_486_bus.vhd
100vhdl_example/35_486_bus/35_486_sys.vhd
100vhdl_example/35_486_bus/35_bit_pack.vhd
100vhdl_example/35_486_bus/35_bus_test.vhd
100vhdl_example/35_486_bus/35_ram_controller.vhd
100vhdl_example/35_486_bus/75_RAM.VHD
100vhdl_example/35_486_bus/README.TXT
100vhdl_example/36_GCD/36_GCD.VHD
100vhdl_example/36_GCD/36_TEST.VHD
100vhdl_example/36_GCD/README.TXT
100vhdl_example/37_test_105/37_test_105.vhd
100vhdl_example/38_test_28/38_Test_28.vhd
100vhdl_example/39_wst0dp/39_wst0dp.vhd
100vhdl_example/39_wst0dp/README.TXT
100vhdl_example/3_MUL/3_MUL.VHD
100vhdl_example/3_MUL/README.TXT
100vhdl_example/40_generic_dec/40_generic_dec.vhd
100vhdl_example/40_generic_dec/README.TXT
100vhdl_example/41_generic_testbench/40_generic_dec.vhd
100vhdl_example/41_generic_testbench/41_generic_testbench.vhd
100vhdl_example/41_generic_testbench/README.TXT
100vhdl_example/42_MIX/42_MIX.VHD
100vhdl_example/42_MIX/README.TXT
100vhdl_example/43_register/43_shift_reg.vhd
100vhdl_example/43_register/43_test_register.vhd
100vhdl_example/43_register/README.TXT
100vhdl_example/44_reg_counter/44_MVL7_functions.vhd
100vhdl_example/44_reg_counter/44_reg_counter.vhd
100vhdl_example/44_reg_counter/44_synthesis_types.vhd
100vhdl_example/44_reg_counter/44_test_vector.vhd
100vhdl_example/44_reg_counter/44_TYPES.VHD
100vhdl_example/44_reg_counter/README.TXT
100vhdl_example/45_test_63/45_test_63.vhd
100vhdl_example/46_generic/46_default_generic.vhd
100vhdl_example/46_generic/README.TXT
100vhdl_example/47_CONST/47_const_test.vhd
100vhdl_example/48_test_18e/48_test_18e.vhd
100vhdl_example/49_DELTA/49_TEST.VHD
100vhdl_example/4_COMP/4_COMP.VHD
100vhdl_example/4_COMP/README.TXT
100vhdl_example/50_test_18e/50_test_18e.vhd
100vhdl_example/51_te
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