32bit_RISC_CPU/32位RISC处理器软核的设计与验证.doc
32bit_RISC_CPU/alu_test.v
32bit_RISC_CPU/cpu.v
32bit_RISC_CPU/cpu_1.0.pdf
32bit_RISC_CPU/cpu_verilog/alu.v
32bit_RISC_CPU/cpu_verilog/cntrl_rf.v
32bit_RISC_CPU/cpu_verilog/cpu.v
32bit_RISC_CPU/cpu_verilog/dcache_top.v
32bit_RISC_CPU/cpu_verilog/decode.v
32bit_RISC_CPU/cpu_verilog/forward.v
32bit_RISC_CPU/cpu_verilog/interrupt.v
32bit_RISC_CPU/cpu_verilog/mpu.v
32bit_RISC_CPU/cpu_verilog/pc_gen.v
32bit_RISC_CPU/cpu_verilog/regfile.v
32bit_RISC_CPU/cpu_verilog/reg_ex.v
32bit_RISC_CPU/cpu_verilog/reg_id.v
32bit_RISC_CPU/cpu_verilog/reg_if.v
32bit_RISC_CPU/cpu_verilog/reg_mem.v
32bit_RISC_CPU/cpu_verilog/write_back.v
32bit_RISC_CPU/POTATO_TEST/cpu_summary.html
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/alu.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/cntrl_rf.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/cpu.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/dcache_top.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/decode.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/forward.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/interrupt.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/mpu.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/pc_gen.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/regfile.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/reg_ex.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/reg_id.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/reg_if.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/reg_mem.v
32bit_RISC_CPU/POTATO_TEST/cpu_verilog/write_back.v
32bit_RISC_CPU/POTATO_TEST/dcache_top_summary.html
32bit_RISC_CPU/POTATO_TEST/isim/work/addr__decoder/addr__decoder.h
32bit_RISC_CPU/POTATO_TEST/isim/work/addr__decoder/mingw/addr__decoder.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/alu/alu.h
32bit_RISC_CPU/POTATO_TEST/isim/work/alu/mingw/alu.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/cntrl__rf/cntrl__rf.h
32bit_RISC_CPU/POTATO_TEST/isim/work/cntrl__rf/mingw/cntrl__rf.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/cpu/cpu.h
32bit_RISC_CPU/POTATO_TEST/isim/work/cpu/mingw/cpu.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/dcache/dcache.h
32bit_RISC_CPU/POTATO_TEST/isim/work/dcache/mingw/dcache.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/dcache__top/dcache__top.h
32bit_RISC_CPU/POTATO_TEST/isim/work/dcache__top/mingw/dcache__top.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/decode/decode.h
32bit_RISC_CPU/POTATO_TEST/isim/work/decode/mingw/decode.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/dram/dram.h
32bit_RISC_CPU/POTATO_TEST/isim/work/dram/mingw/dram.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/flash__wbbus/flash__wbbus.h
32bit_RISC_CPU/POTATO_TEST/isim/work/flash__wbbus/mingw/flash__wbbus.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/forward/forward.h
32bit_RISC_CPU/POTATO_TEST/isim/work/forward/mingw/forward.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/glbl/glbl.h
32bit_RISC_CPU/POTATO_TEST/isim/work/glbl/mingw/glbl.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/hdllib.ref
32bit_RISC_CPU/POTATO_TEST/isim/work/hdpdeps.ref
32bit_RISC_CPU/POTATO_TEST/isim/work/icache/icache.h
32bit_RISC_CPU/POTATO_TEST/isim/work/icache/mingw/icache.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/interrupt/interrupt.h
32bit_RISC_CPU/POTATO_TEST/isim/work/interrupt/mingw/interrupt.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/mpu/mingw/mpu.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/mpu/mpu.h
32bit_RISC_CPU/POTATO_TEST/isim/work/pc__gen/mingw/pc__gen.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/pc__gen/pc__gen.h
32bit_RISC_CPU/POTATO_TEST/isim/work/prom/mingw/prom.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/prom/prom.h
32bit_RISC_CPU/POTATO_TEST/isim/work/regfile/mingw/regfile.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/regfile/regfile.h
32bit_RISC_CPU/POTATO_TEST/isim/work/reg__ex/mingw/reg__ex.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/reg__ex/reg__ex.h
32bit_RISC_CPU/POTATO_TEST/isim/work/reg__id/mingw/reg__id.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/reg__id/reg__id.h
32bit_RISC_CPU/POTATO_TEST/isim/work/reg__if/mingw/reg__if.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/reg__if/reg__if.h
32bit_RISC_CPU/POTATO_TEST/isim/work/reg__mem/mingw/reg__mem.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/reg__mem/reg__mem.h
32bit_RISC_CPU/POTATO_TEST/isim/work/sdram__wbbus/mingw/sdram__wbbus.obj
32bit_RISC_CPU/POTATO_TEST/isim/work/sdram__wbbus/sdram__wbbus.h
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg0A/alu.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg11/wb__arbiter.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg15/forward.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg29/interrupt.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg2D/glbl.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg32/reg__ex.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg32/reg__id.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg33/write__back.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg34/reg__if.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg3C/pc__gen.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg3D/sdram__wbbus.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg3E/cntrl__rf.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg42/wb__connect.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg47/_t_e_s_t___c_p_u.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg48/dram.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg4A/mpu.bin
32bit_RISC_CPU/POTATO_TEST/isim/work/vlg4C/fla