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文件名称:lab2

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    2012-11-16
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    5.47mb
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基于Xilinx-XUPV2P开发平台的嵌入式系统实验例程:实验2为硬件设计添加IP-Xilinx-XUPV2P-based development platform for embedded systems experimental routines: Experiment 2 for the hardware design to add IP
相关搜索: xupv2p lab2

(系统自动生成,下载前可以参看下载内容)

下载文件列表

lab2/automake.log
lab2/bitinit.log
lab2/blkdiagram/.dswkshop/ds_Report.css
lab2/blkdiagram/.dswkshop/ds_Report.js
lab2/blkdiagram/.dswkshop/IMG_closeBranch.gif
lab2/blkdiagram/.dswkshop/IMG_openBranch.gif
lab2/blkdiagram/.dswkshop/MdtXdsGen_HTMLDatasheet.css
lab2/blkdiagram/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl
lab2/blkdiagram/.dswkshop/MdtXdsGen_HTMLIPSection.xsl
lab2/blkdiagram/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl
lab2/blkdiagram/.dswkshop/MdtXdsGen_HTMLPeripherals.xsl
lab2/blkdiagram/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl
lab2/blkdiagram/.dswkshop/MdtXdsSVG_BlkDBifDefs.xsl
lab2/blkdiagram/.dswkshop/MdtXdsSVG_BlkdBusses.xsl
lab2/blkdiagram/.dswkshop/MdtXdsSVG_BlkdIOPorts.xsl
lab2/blkdiagram/.dswkshop/MdtXdsSVG_BlkDModuleDefs.xsl
lab2/blkdiagram/.dswkshop/MdtXdsSVG_BlkDPeripherals.xsl
lab2/blkdiagram/.dswkshop/MdtXdsSVG_BlkdProcessors.xsl
lab2/blkdiagram/.dswkshop/MdtXdsSVG_BlockDiagram.xsl
lab2/blkdiagram/.dswkshop/MdtXdsSVG_Colors.xsl
lab2/blkdiagram/.dswkshop/MdtXdsSVG_Render.css
lab2/blkdiagram/.dswkshop/svg10.dtd
lab2/blkdiagram/.dswkshop/_exsi_tmp.xml
lab2/blkdiagram/MdtXdsSVG_Render.css
lab2/blkdiagram/svg10.dtd
lab2/blkdiagram/system.html
lab2/blkdiagram/system.jpg
lab2/blkdiagram/system.svg
lab2/data/system.ucf
lab2/data/system0.ucf
lab2/data/新建 文本文档.txt
lab2/etc/bitgen.ut
lab2/etc/download.cmd
lab2/etc/fast_runtime.opt
lab2/hdl/dcm_0_wrapper.vhd
lab2/hdl/dip_push_wrapper.vhd
lab2/hdl/elaborate/plb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/verilog/plb_bram_if_cntlr_1_bram_elaborate.v
lab2/hdl/elaborate/plb_bram_if_cntlr_1_bram_elaborate_v1_00_a/hdl/vhdl/plb_bram_if_cntlr_1_bram_elaborate.vhd
lab2/hdl/elaborate/plb_bram_if_cntlr_2_bram_elaborate_v1_00_a/hdl/verilog/plb_bram_if_cntlr_2_bram_elaborate.v
lab2/hdl/elaborate/plb_bram_if_cntlr_2_bram_elaborate_v1_00_a/hdl/vhdl/plb_bram_if_cntlr_2_bram_elaborate.vhd
lab2/hdl/jtagppc_0_wrapper.vhd
lab2/hdl/opb_wrapper.vhd
lab2/hdl/plb2opb_wrapper.vhd
lab2/hdl/plb_bram_if_cntlr_1_bram_wrapper.vhd
lab2/hdl/plb_bram_if_cntlr_1_wrapper.vhd
lab2/hdl/plb_bram_if_cntlr_2_bram_wrapper.vhd
lab2/hdl/plb_bram_if_cntlr_2_wrapper.vhd
lab2/hdl/plb_wrapper.vhd
lab2/hdl/ppc405_0_wrapper.vhd
lab2/hdl/ppc405_1_wrapper.vhd
lab2/hdl/reset_block_wrapper.vhd
lab2/hdl/rs232_uart_1_wrapper.vhd
lab2/hdl/system.vhd
lab2/implementation/bitgen.ut
lab2/implementation/cache/cache.cat
lab2/implementation/cache/dcm_0_wrapper.ngc
lab2/implementation/cache/dip_push_wrapper.ngc
lab2/implementation/cache/jtagppc_0_wrapper.ngc
lab2/implementation/cache/opb_wrapper.ngc
lab2/implementation/cache/plb2opb_wrapper.ngc
lab2/implementation/cache/plb_bram_if_cntlr_1_bram_wrapper.ngc
lab2/implementation/cache/plb_bram_if_cntlr_1_wrapper.ngc
lab2/implementation/cache/plb_bram_if_cntlr_2_bram_wrapper.ngc
lab2/implementation/cache/plb_bram_if_cntlr_2_wrapper.ngc
lab2/implementation/cache/plb_wrapper.ngc
lab2/implementation/cache/ppc405_0_wrapper.ngc
lab2/implementation/cache/ppc405_1_wrapper.ngc
lab2/implementation/cache/reset_block_wrapper.ngc
lab2/implementation/cache/rs232_uart_1_wrapper.ngc
lab2/implementation/dcm_0_wrapper/dcm_0_wrapper.ngc
lab2/implementation/dcm_0_wrapper.ngc
lab2/implementation/dip_push_wrapper/dip_push_wrapper.ngc
lab2/implementation/dip_push_wrapper.ngc
lab2/implementation/download.bit
lab2/implementation/fpga.flw
lab2/implementation/jtagppc_0_wrapper/jtagppc_0_wrapper.ngc
lab2/implementation/jtagppc_0_wrapper.ngc
lab2/implementation/netlist.lst
lab2/implementation/opb_wrapper/opb_wrapper.ngc
lab2/implementation/opb_wrapper.ngc
lab2/implementation/plb2opb_wrapper/plb2opb_wrapper.ngc
lab2/implementation/plb2opb_wrapper.ngc
lab2/implementation/plb_bram_if_cntlr_1_bram_wrapper/plb_bram_if_cntlr_1_bram_wrapper.ngc
lab2/implementation/plb_bram_if_cntlr_1_bram_wrapper.ngc
lab2/implementation/plb_bram_if_cntlr_1_wrapper/plb_bram_if_cntlr_1_wrapper.ngc
lab2/implementation/plb_bram_if_cntlr_1_wrapper.ngc
lab2/implementation/plb_bram_if_cntlr_2_bram_wrapper/plb_bram_if_cntlr_2_bram_wrapper.ngc
lab2/implementation/plb_bram_if_cntlr_2_bram_wrapper.ngc
lab2/implementation/plb_bram_if_cntlr_2_wrapper/plb_bram_if_cntlr_2_wrapper.ngc
lab2/implementation/plb_bram_if_cntlr_2_wrapper.ngc
lab2/implementation/plb_wrapper/plb_wrapper.ngc
lab2/implementation/plb_wrapper.ngc
lab2/implementation/ppc405_0_wrapper/ppc405_0_wrapper.ngc
lab2/implementation/ppc405_0_wrapper.ngc
lab2/implementation/ppc405_1_wrapper/ppc405_1_wrapper.ngc
lab2/implementation/ppc405_1_wrapper.ngc
lab2/implementation/reset_block_wrapper/reset_block_wrapper.ngc
lab2/implementation/reset_block_wrapper.ngc
lab2/implementation/rs232_uart_1_wrapper/rs232_uart_1_wrapper.ngc
lab2/implementation/rs232_uart_1_wrapper.ngc
lab2/implementation/system.bgn
lab2/implementation/system.bit
lab2/implementation/system.bld
lab2/implementation/system.bmm
lab2/implementation/system.drc
lab2/implementation/system.ncd
lab2/implementation/system.ngc
lab2/implementation/system.ngd
lab2/implementation/system.pad
lab2/implementation/system.par
lab2/implementation/system.pcf
lab2/implementation/system.twr
lab2/implementation/system.twx
lab2/implementation/system.ucf
lab2/imple

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